Memory Stick Transmit Fifo Data Register - Motorola DragonBall MC9328MX1 Reference Manual

Table 21-8. Memory Stick Control/Status Register Description (Continued)
Name
BSYCNT Busy Count—Sets the maximum BSY time-out time to
Bits 10–8 wait until the RDY signal is output from the card. RDY
time-out error detection is not performed when
BSYCNT = 0 and exceeding 5 × 4 + 2 = 22 SCLK
cycles causes a RDY time-out error.
INT Interrupt Status—Indicates whether an interrupt
Bit 7 condition was generated. The status will change even
when the interrupt itself is disabled via the INTEN bit of
the MSICS register.
DRQ DMA Request—Indicates that data was requested.
Bit 6 The status will change even when the interrupt itself is
disabled via the DRQEN bit of the MSICS register.
Reserved Reserved—These bits are reserved and should read 0.
Bits 5–4
RBE Receive Buffer Empty Flag—Indicates whether there
Bit 3 is data in the receive buffer or not.
RBF Receive Buffer Full Flag—Indicates whether the
Bit 2 receive buffer is full or not.
TBE Transmit Buffer Empty Flag—Indicates whether there
Bit 1 is data in the transmit buffer or not.
TBF Transmit Buffer Full Flag—Indicates whether the
Bit 0 transmit buffer is full or not.

21.7.2 Memory Stick Transmit FIFO Data Register

The write-only Memory Stick Transmit FIFO Data Register is a 16-bit register. The bit position
assignments for this register are shown in the following register display. The settings for this register are
described in Table 21-9.
This register's value and the FIFO pointers are initialized on power up or when RST bit of Memory Stick
Control/Status Register is 1.
Big/little endian mode of the FIFO DATA register can be set by the LEND bit of the MSC2 register. The
default setting is big-endian. When the LEND bit is 0, the MSHC module handles the FIFO data in
big-endian. In big-endian mode, to send only one byte of data, the data byte must be written in bits 15
through 8. When the LEND bit is 1, the MSHC module handles the FIFO data in little-endian. In
little-endian mode, to send only one byte of data, the data byte must be written in bits 7 through 0.
When TBF is 1, write data is ignored and it is not stored to the FIFO. The Transmit FIFO DATA register
must be written only when the MSCS register's DRQ bit or MSICS register's DRQ bit is 1, and must not
be written before setting a write command to the Memory Stick Command Register.
MOTOROLA
Description
Memory Stick Host Controller (MSHC) Module
Memory Stick Command Register
Setting
000 = No RDY time-out error detection
performed
001 = 1 × 4 + 2 = 6 SCLK
010 = 2 × 4 + 2 = 10 SCLK
011 = 3 × 4 + 2 = 14 SCLK
100 = 4 × 4 + 2 = 18 SCLK
101 = 5 × 4 + 2 = 22 SCLK
110 = 6 × 4 + 2 = 26 SCLK
111 = 7 × 4 + 2 = 30 SCLK
0 = No interrupt condition occurred
1 = Interrupt condition occurred
0 = No DMA request occurred
1 = DMA request occurred
0 = Data available in receiver data buffer
1 = Receiver data buffer EMPTY
0 = Receiver data buffer NOT FULL
1 = Receiver data buffer FULL
0 = Data in the transmit data buffer
1 = Transmit data buffer EMPTY
0 = Transmit data buffer NOT FULL
1 = Transmit data buffer FULL
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