Arm920T Macrocell; Caches; Figure 4-1 Arm920T Core Functional Block Diagram - Motorola DragonBall MC9328MX1 Reference Manual

ARM920T Processor
Figure 4-1. ARM920T Core Functional Block Diagram

4.2 ARM920T Macrocell

The ARM920T macrocell is based on the ARM9TDMI™ Harvard architecture processor core, with an
efficient 5-stage pipeline. The architecture of the processor core or integer unit is described in more detail
later in this chapter.
To reduce the effect of main memory bandwidth and latency on performance, the ARM920T processor
includes:
• Instruction cache
• Data cache
• MMU
• TLBs
• Write buffer
• Physical address TAG RAM

4.2.1 Caches

Two 16 kbyte caches are implemented, one for instructions, the other for data, both with an 8-word line
size. A 32-bit data bus connects each cache to the ARM9TDMI core allowing a 32-bit instruction to be
fetched and fed into the instruction Decode stage of the pipeline at the same time as a 32-bit data access for
the Memory stage of the pipeline.
4-2 MC9328MX1 Reference Manual MOTOROLA