Table 19-21 Refresh Mode Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

19.4.13 Refresh Mode Control Register
The Refresh Mode Control Register is used to control refresh characteristics.
RMCR
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Table 19-21. Refresh Mode Control Register Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–2
LCDC_EN LCDC Enable—Enables/Disables the LCDC.
Bit 1
SELF_REF Self-Refresh—Enables/Disables self-refresh mode.
Bit 0
1. On entering self-refresh mode, the LSCLK and LD [15:0] signals stay low. HYSN and VSYN
operate normally.
2. Except for the SSA and Mapping RAM registers, all configurations must be performed
before enabling the LCDC to avoid a malfunction.
3. The SSA must always match the address range of the RAM selected. If the user wants to
switch between various types of RAM, the LCDC must be disabled before switching.
MOTOROLA
Refresh Mode Control Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
r r r r
0 0 0 0
Description
NOTE:
LCD Controller
24 23 22 21
r r r r
0 0 0 0
0x0000
8 7 6 5
r r r r
0 0 0 0
0x0000
0 = Disable the LCDC
1 = Enable the LCDC
0 = Disable self-refresh
1 = Enable self-refresh
Programming Model
Addr
0x00205034
20 19 18 17
r r r r
0 0 0 0
4 3 2 1
LCDC SELF
_EN _REF
r r r rw
0 0 0 0
Settings
19-33
16
r
0
0
rw
0