Motorola DragonBall MC9328MX1 Reference Manual page 218

External Interface Module (EIM)
Table 11-5. Chip Select Control Registers Description (Continued)
Name
BCS Burst Clock Start—Determines the number of
Bits 59–56 half cycles after LBA assertion before the first
rising edge of BCLK is seen. A value of 0 results
in a half clock delay, not an immediate assertion.
When the BCM bit is set (BCM = 1) in the EIM
configuration register, this overrides the BCS bits.
BCS is cleared by a hardware reset.
PSZ Page Size—Indicates the number of words
Bits 55–54 (where "word" is defined by the port size or DSZ
bits) in a page in memory. This ensures that the
EIM does not burst past a page boundary when
the PME bit is set.
PSZ is cleared by a hardware reset.
PME Page Mode Emulation—Enables/Disables page
Bit 53 mode emulation in burst mode. When PME is set,
the external address asserts for each piece of
data requested. Additionally, the LBA and BCLK
signals behave as they do when an asynchronous
access is performed.
PME is cleared by a hardware reset.
SYNC Synchronous Burst Mode
Bit 52 Enable—Enables/Disables synchronous burst
mode. When enabled, the EIM is capable of
interfacing to burstable flash devices through
additional burst control signals: BCLK, LBA, and
ECB. The sequencing of these additional I/Os is
controlled by other EIM configuration register bit
settings as defined below.
SYNC is cleared by a hardware reset.
DOL Data Output Length—Specifies the expected
Bits 51–48 number of system clock cycles required for burst
read data to be valid on the data bus before it is
latched by the EIM. The reset value specifies that
burst data is held for a single system clock period.
As system clock frequencies increase, it may
become necessary to delay sampling the data for
multiple system clock periods to meet burst flash
max frequency specifications and/or EIM data
setup time requirements. DOL has no effect on
EIM data latching when SYNC = 0.
DOL is cleared by a hardware reset.
11-14
Description
MC9328MX1 Reference Manual
Settings
0000 = 1 half cycle before BCLK
0001 = 2 half cycles before BCLK
...
1111 = 16 half cycles before BCLK
00 = 4 words in a page
01 = 8 words in a page
10 = 16 words in a page
11 = 32 words in a page
0 = Disables page mode emulation
1 = Enables page mode emulation
0 = Disables synchronous burst mode
1 = Enables synchronous burst mode
0000 = 2 system clock delays
0001 = 2 system clock delays
0010 = 3 system clock delays
0011 = 4 system clock delays
...
1111 = 16 system clock delays
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