Table 30-8 I2S Mode Selection - Motorola DragonBall MC9328MX1 Reference Manual

Integrated portable system processor
Table of Contents

Advertisement

Table 30-7. SSI Control/Status Register Description (Continued)
Name
TFE
Transmit FIFO Empty—Indicates that the data level in the
Bit 0
transmit FIFO reaches the Transmit FIFO Empty Water Mark.
The Water Mark is defined in the TFWM field of the SSI FIFO
Control/Status Register (SFCSR). The transmit FIFO must be
enabled or TFE is meaningless.
When TFE is set, data can be written to the transmit FIFO via the
STX register.
Note: An interrupt is generated only when both the TFE and
TIE (of the STCR) are set and the transmit FIFO is enabled (the
TFEN bit in the STCR is set).
2
30.3.7.1 I
S Mode Selection
The SCSR contains two bits, the I
mode of the SSI module. This section explains how the mode of the module affects the bits in the other SSI
registers. Table 30-8 summarizes the mode settings.
In normal mode operation, no register bits are forced to any particular state internally and the SSI can be
programmed to work in any operating condition.
2
When entering I
S modes (I
to write to these bits when in I
Table 30-9.
The user must configure the bit clock in the STCCR and the SRCCR.
2
I
S Mode
Master or save
Master or save
Master or save
Master or save
Master or save
MOTOROLA
Description
2
S Mode Select (I2S MODE1 and I2S MODE0) bits, that determine the
Table 30-8. I
I2S_MODE [1]
I2S_MODE [0]
0
0
1
1
2
2
S master or I
S slave), several control bits are fixed in the hardware. Attempts
2
2
S master or I
S slave mode are ignored. These bits are described in
2
Table 30-9. I
S Master or I
Bit
Register
Forced
Name
Location
Value
SYN
SCSR [12]
NET
SCSR [11]
TSHFD
STCR [4]
RSHFD
SRCR [4]
TSCKP
STCR [3]
Synchronous Serial Interface (SSI)
2
S Mode Selection
Remark
0
Normal mode
1
2
I
S master mode
0
2
I
S slave mode
1
Normal mode
2
S Slave Mode Settings
Function
1
Synchronous mode enabled
1
Network mode enabled
0
Transmission direction is MSB first
0
Receive direction is MSB first
1
Falling edge of bit clock clocks data out
Programming Model
Settings
0 = Data level in the transmit
FIFO exceeds Water
Mark
1 = Data level in the transmit
FIFO below Watermark
30-19

Advertisement

Table of Contents
loading

Table of Contents