Figure 24-53 Sdram Power-On Initialization Sequence - Motorola DragonBall MC9328MX1 Reference Manual

6. SDRAM is now ready for normal operation.
The SDRAM Controller accomplishes steps 1 and 2 in hardware, however it relies on software assistance
to complete the remaining actions. The 200 µs stabilization period is guaranteed by the use of 2 reset
signals whose negations are separated by this amount. An SDRAM reset signal (SD_RST) is asserted to
coincide with the system reset used by the rest of the chip, however it negates 200 ms prior to the negation
of system reset. The SDRAM Controller leaves the SDRAM arrays in a NOP condition following the
negation of the DRAM reset. Figure 24-53 shows the SDRAM Power-on initialization sequence.
VCC
SYSTEM
CLOCK
DRAM
RESET
HARD_ASYN_
RESET
SDCLK
SDRAM
COMMAND
Figure 24-53. SDRAM Power-On Initialization Sequence
Following negation of system reset, initialization software must complete steps 3 through 5 using the
special operating modes enabled by the SMODE field in the SDRAM Control Register. To precharge the
SDRAM array, the SDRAM Controller operating mode is set to "precharge command" and an access is
made to the SDRAM address range with address bit A10 = 1. Instead of running a normal read or write
cycle, the controller issues a precharge all command to the addressed array. The operating mode is then
switched to "auto-refresh" and 8 accesses are made to the SDRAM address space. Each of the accesses
results in a refresh command to the addressed array. A "mode register set" command is required to
complete the initialization sequence. The value written is system dependent. Consult Section 24.8.4,
"Mode Register Programming," for details. Finally, the controller is placed back in the normal mode of
operation so that subsequent accesses to the address space result in normal read and write cycles to the
SDRAM array.
Although the initialization sequence described in the previous paragraphs is only required at power-on, it
may be repeated at any time the programmer deems necessary.
Code Example 24-2 on page 24-58 provides the code necessary for the initialization sequence.
MOTOROLA
200 µs Minimum
PRE AUTO AUTO
NOP
ALL REF REF
SDRAM Software Initialization Sequence
SDRAM Memory Controller
AUTO AUTO AUTO AUTO AUTO
REF REF REF REF REF
SDRAM Operation
AUTO MODE
NORMAL
REF SET
24-57