Passive Panel Interface Timing; Figure 19-11 Lcdc Interface Timing For 8-Bit Data Passive Matrix Color Panels - Motorola DragonBall MC9328MX1 Reference Manual

FLM
LINE 1
LP
LP
LSCLK
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0
Figure 19-11. LCDC Interface Timing for 8-bit Data Passive Matrix Color Panels

19.3.8.3 Passive Panel Interface Timing

Figure 19-12 shows the horizontal timing (timing of one line), including both the line pulse (LP) and the
data. The width of LP and delays both before and after LP are programmable. The parameters used for
panel interface timing are:
• XMAX (X size) defines the number of pixels per line. XMAX is the total number of pixels per line.
• H_WAIT_1 defines the delay from the end of data output to the beginning of LP.
• H_WIDTH (horizontal sync pulse width) defines the width of the FLM pulse, and H_WIDTH must
be at least 1.
• H_WAIT_2 defines the delay from the end of LP to the beginning of data output.
All parameters are defined in unit of pixel clock period, unless stated
otherwise.
MOTOROLA
LINE 2 LINE 3 LINE 4
1 2 3
R[0,0] B[0,2] G[0,5]
G[0,0] R[0,3] B[0,5]
B[0,0] G[0,3] R[0,6]
R[0,1] B[0,3] G[0,6]
G[0,1] R[0,4] B[0,6]
B[0,1] G[0,4] R[0,7]
R[0,2] B[0,4] G[0,7]
G[0,2] R[0,5] B[0,7]
NOTE:
LCD Controller
LINE n LINE 1
89 90 3*m/8-1
B[0,234] G[0,237] B[0,m-6] G[0,m-3]
R[0,235] B[0,237] R[0,m-5] B[0,m-3]
G[0,235] R[0,238] G[0,m-5] R[0,m-2]
B[0,235] G[0,238] B[0,m-5] G[0,m-2]
R[0,236] B[0,238] R[0,m-4] B[0,m-2]
G[0,236] R[0,239] G[0,m-4] R[0,m-1]
B[0,236] G[0,239] B[0,m-4] G[0,m-1]
R[0,237] B[0,239] R[0,m-3] B[0,m-1]
LCDC Operation
3*m/8
19-13