Self-Refresh; Self-Refresh During Reset_In; Self-Refresh During Low-Power Mode; Powerdown Operation During Reset And Low-Power Modes - Motorola DragonBall MC9328MX1 Reference Manual

32KHz
Internal
Address
Bus
Internal R/W
SDCLK
ADDR
RAS,
CAS,
SDWE
CSDx
DATA
Figure 24-28. Hardware Refresh With Pending Bus Cycle Timing Diagram

24.7.3 Self-Refresh

SDRAM data must be retained during assertion of system reset (RESET_IN) and power conservation
modes if refresh has been enabled. The SDRAM Controller detects these conditions and places the
memory in self-refresh. If refresh has not been enabled, the SDRAM Controller places the memories in a
lower power consumption mode known as Powerdown. This operation is described in Section 24.7.3.3,

"Powerdown Operation During Reset and Low-Power Modes."

24.7.3.1 Self-Refresh During RESET_IN

The assertion of system reset (RESET_IN) triggers the SDRAM Controller to place the memory in
self-refresh provided refresh had been previously enabled. Refresh during system reset is disabled by an
SDRAM Controller reset. It remains disabled until the refresh rate is programmed to a non-zero value.
Once enabled, self-refresh is invoked anytime system reset is asserted without a corresponding SDRAM
reset.

24.7.3.2 Self-Refresh During Low-Power Mode

If refresh is enabled, low-power mode also forces the SDRAM into self-refresh mode. When the SDRAM
Controller detects that the bus masters are entering a low-power condition it begins a self-refresh sequence
once any in-progress bus access has completed. A Precharge All command is issued to close any open
memory pages, the Self-Refresh command is issued, and the clock enable is brought low. Once the
memories are safely in their low-power state, the SDRAMC tells the system clock controller to enter sleep
mode.
24.7.3.3 Powerdown Operation During Reset and Low-Power Modes
The powerdown mode is used instead of self-refresh whenever system reset or any of the low-power
modes occur and refresh has not been enabled. This memory operating mode does not remove power, as
the name might imply. It simply lowers power consumption by disabling the clock input buffer and halting
all internal activity. Because powerdown can only be entered if all banks are idle, a Precharge All
command must be issued to the memories prior to stopping the clock. Figure 24-31 illustrates the
powerdown sequence following assertion of system reset.
MOTOROLA
SDRAMx
t (Minimum)
RP
PRE-ALL
SDRAM Memory Controller
>= t (Minimum)
RC
REF A
General Operation
ROWx
ACT
24-33