Programming And Reading Etm Registers; Pin Configuration For Etm; Table 5-1 Etm Pin Configuration - Motorola DragonBall MC9328MX1 Reference Manual

Embedded Trace Macrocell (ETM)

5.2 Programming and Reading ETM Registers

All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor's TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit
shift register comprising:
• 32-bit data field
• 7-bit address field
• A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address
field, and 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit
data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.
For further details of ETM registers, see the Embedded Trace Macrocell specification.

5.3 Pin Configuration for ETM

The ETM module uses 13 pins on the MC9328MX1. These pins are multiplexed with other functions on
the device, and must be configured for ETM operation. Table 5-1 identifies the pin configuration, however,
only the 5 pins of the 13 that are multiplexed are shown.
The user must ensure that the data direction bits in the GPIO are set to the
correct direction for proper operation. See Section 32.5.1, "Data Direction
Registers," on page 32-9 for details.
Pin
ETMTRACESYNC Alternate function of
GPIO Port A [0]
ETMTRACECLK Alternate function of
GPIO Port A [31]
ETMPIPESTAT Alternate function of
[2:0] GPIO Port A [30:28]
ETMTRACEPKT Alternate function of
[7:4] GPIO Port A [20:17]
ETMTRACEPKT Alternate function of
[3:0] GPIO Port A [27:24]
5-2
NOTE:
Table 5-1. ETM Pin Configuration
Setting
1. Clear bit 0 of Port A GPIO In Use Register (GIUS_A)
2. Set bit 0 of Port A General Purpose Register (GPR_A)
1. Clear bit 31 of Port A GPIO In Use Register (GIUS_A)
2. Set bit 31 of Port A General Purpose Register (GPR_A)
1. Clear bits [30:28] of Port A GPIO In Use Register (GIUS_A)
2. Set bits [30:28] of Port A General Purpose Register (GPR_A)
1. Clear bits [20:17] of Port A GPIO In Use Register (GIUS_A)
2. Set bits [20:17] of Port A General Purpose Register (GPR_A)
1. Clear bits [27:24] of Port A GPIO In Use Register (GIUS_A)
2. Set bits [27:24] of Port A General Purpose Register (GPR_A)
MC9328MX1 Reference Manual
Configuration Procedure
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