Mma Mac Burst Count Register; Mma Mac Bit Select Register; Table 17-10 Mma Mac Burst Count Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Multimedia Accelerator (MMA)

17.3.1.9 MMA MAC Burst Count Register

MMA_MAC_BURST
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Table 17-10. MMA MAC Burst Count Register Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–8
BURST COUNT Memory Access Burst Count—Determines the maximum number of read accesses to
Bits 7–0 memory allowed in one burst. This feature ensures that the MMA does not hold the memory
bus for too long.

17.3.1.10 MMA MAC Bit Select Register

MMA_MAC_BITSEL
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
17-14
MMA MAC Burst Count Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
r r r r
0 0 0 0
MMA MAC Bit Select Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
r r r r
0 0 0 0
MC9328MX1 Reference Manual
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
BURST COUNT
r rw rw rw rw
0 0 0 0 0
0x0000
Description
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
r r r r r
0 0 0 0 0
0x0000
Addr
0x00222020
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
rw rw rw rw
0 0 0 0
Addr
0x00222024
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
BITSEL
r rw rw rw
0 0 0 0
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