Motorola DragonBall MC9328MX1 Reference Manual page 954

MMC/SD clock rate register, see CLK_RATE register
MMC/SD command and data control register,
see CMD_DAT_CONT register
MMC/SD higher argument register, see ARGH register
MMC/SD interrupt mask register,
see INT_MASK register
MMC/SD lower argument register, see ARGL register
MMC/SD number of blocks register, see NOB register
MMC/SD read time out register, see READ_TO register
MMC/SD response fifo register, see RES_FIFO register
MMC/SD response time out register,
see RES_TO register
MMC/SD revision number register,
see REV_NO register
MMC/SD status register, see STATUS register
MOD ENAB bit, 17-7
MPCTL0 register
MFD field, 12-10
MFI field, 12-10
MFN field, 12-10
PD field, 12-10
MPCTL0 register, 12-10
MPCTL1 register
BRMO bit, 12-11
MPCTL1 register, 12-11
MSACD register
ADATASIZE field, 21-21
APID field, 21-21
MSACD register, 21-21
MSC2 register
ACD bit, 21-20
LEND bit, 21-20
MSCEN bit, 21-20
RED bit, 21-20
MSC2 register, 21-20
MSCLKD register
DIV field, 21-23
SRC bit, 21-23
MSCLKD register, 21-22
MSCMD register
DATA SIZE field, 21-13
PID field, 21-13
MSCMD register, 21-13
MSCS register
BSYCNT field, 21-15
DAKEN bit, 21-14
DRQ bit, 21-15
INT bit, 21-15
NOCRC bit, 21-14
PWS bit, 21-14
RBE bit, 21-15
RBF bit, 21-15
RST bit, 21-14
SIEN bit, 21-14
Index-xii
TBE bit, 21-15
TBF bit, 21-15
MSCS register, 21-14
MSDRQC register
DRQEN bit, 21-24
RFF bit, 21-24
TFE bit, 21-24
MSDRQC register, 21-23
MSFAECS register
FAEEN bit, 21-22
RUN bit, 21-22
TOV bit, 21-22
MSFAECS register, 21-21
MSHC
auto command function, 21-9
block diagram and description, 21-1
bus state control operation, 21-5
data FIFO operation, 21-4
interrupt sources, 21-5
memory stick interface, 21-2
operation, 21-4
overview, 21-1
pin configuration, 21-3
power save mode operation, 21-8
programmer's reference, 21-24
programming model, 21-12
protocol error, 21-28
protocol, 21-26
reset operation, 21-7
serial clock divider operation, 21-11
serial interface overview, 21-24
signal description, 21-3
signal timing, 21-30
system-level DMA transfer operation, 21-11
transfer protocol command (TPC), 21-27
MSICS register
CRC bit, 21-18
DRQ bit, 21-18
DRQSL bit, 21-17
FAE bit, 21-18
INTEN bit, 21-17
PIN bit, 21-18
PINEN bit, 21-17
RDY bit, 21-18
SIF bit, 21-18
TOE bit, 21-19
MSICS register, 21-17
MSPPCD register
PIEN0 bit, 21-19
PIEN1 bit, 21-19
XPIN0 bit, 21-20
XPIN1 bit, 21-20
MSPPCD register, 21-19
MC9328MX1 Reference Manual MOTOROLA