Table 25-22 Reset Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

SmartCard Interface Module (SIM)
25.6.14 Reset Control Register
The bit descriptions and settings for the Reset Control Register (RESET_CNTL) are provided in
Table 25-21.
RESET_CNTL
BIT 31 30 29
TYPE r r
0 0 0
RESET
BIT 15 14 13
TYPE r r
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–3
SOFT_RESET Software Reset—Resets the entire SIM. This acts the
Bit 2 same as a hardware reset for the SIM. SOFT_RESET is
self-clearing.
Software must allow a minimum of 4 reference clock cycles
before attempting to access the SIM after a software reset.
FLUSH_XMT Flush Transmitter—Operates as a SIM transmitter reset.
Bit 1 The receive portion of the SIM is not affected. The software
must clear FLUSH_XMT before the SIM transmitter can
operate.
FLUSH_RCV Flush Receiver—Operates as a SIM receiver reset. The
Bit 0 transmit portion of the SIM is not affected. The software
must clear FLUSH_RCV before the SIM receiver can
operate.
25-38
Reset Control Register
28 27 26 25
r r r r r
0 0 0 0
12 11 10 9
r r r r r
0 0 0 0
Table 25-22. Reset Control Register Description
Description
MC9328MX1 Reference Manual
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
r r r r r
0 0 0 0 0
0x0000
0x00211034
19 18 17
r r r
0 0 0
3 2 1
SOFT_ FLUSH_
RESET XMT
r rw rw
0 0 0
Settings
0 = SIM normal operation
1 = SIM held in reset
0 = SIM transmitter normal
operation
1 = SIM transmitter held in reset
0 = SIM receiver normal operation
1 = SIM receiver held in reset
MOTOROLA
Addr
16
r
0
0
FLUSH_
RCV
rw
0