Mmc/Sd Module Interrupt Handling; Logic And Command Interpreters; Figure 20-6 Card Detection Mechanism - Motorola DragonBall MC9328MX1 Reference Manual

Multimedia Card/Secure Digital Host Controller Module (MMC/SD)
CMD3
MMC/SD
Detector
To System IRQ_B
Figure 20-6. Card Detection Mechanism

20.5.2.3 MMC/SD Module Interrupt Handling

Interrupts generated from the MMC/SD module originate from errors or are status indicators. The
MMC/SD module checks response and data CRCs and the internal watchdog timer. An error is generated
when any of those checks fail. Status indicators include response done, transfer done, and FIFO status.
Interrupt masking and generation is handled in the interrupt handler block.

20.5.3 Logic and Command Interpreters

The two interpreters are built similarly and consist of 3 parts: inner state machine, sub-module controller,
and CRC accelerator.
The command controller handles all interrupts related to the command line (SD_CMD) including
command data sequence generation, command response extraction, CRC generation and checking, and
response time-out. A state machine, logic controller, and CRC accelerator control these functions.
20-10 MC9328MX1 Reference Manual MOTOROLA