Serial Clock Divider Operation; System-Level Dma Transfer Operation; Figure 21-6 Mshc Module Serial Clock Divider; Table 21-4 Serial Clock Divider Settings - Motorola DragonBall MC9328MX1 Reference Manual

21.5.7 Serial Clock Divider Operation

The MC9328MX1 MSHC module provides for flexible transfer rate control with a configurable Serial
Clock Divider. Four settings are supported by the Divider: /1, /2, /4, and /8. When internal HCLK is used,
the setting /1 is provided for manufacturer testing and should not be used.
Figure 21-6 illustrates the MSHC module serial clock divider and Table 21-4 provides the settings.
HCLK
internal
MS_SCLKI
external
Source Select Bit
(SRC Bit of MSCLKD)
0
0
0
0
1
1
1
1

21.5.8 System-Level DMA Transfer Operation

The MSHC module DMA request bit is assigned to DMA_REQ [8] in the MC9328MX1 DMA request
signals. Please refer to the Chapter 13, "DMA Controller," more detail information. Table 21-5 on
page 21-12 summarizes the important data of the MSHC module to configure the DMA general and DMA
I/O registers. Because the Rx and Tx share the same memory address, only 1 DMA channel can be used for
DMA transfer—that is, it cannot use 2 DMA channels to handle Rx and Tx separately. This implies that
the every time the MSHC module is switched from the transmit to the receive operation or the vice versa,
the DMA registers need to be reconfigured.
MOTOROLA
SRC
DIV 8
DIV 4
0
DIV 2
1
DIV 1
Figure 21-6. MSHC Module Serial Clock Divider
Table 21-4. Serial Clock Divider Settings
Divide Bits
(DIV [1:0] of MSCLKD)
0:0
0:1
1:0
1:1
0:0
0:1
1:0
1:1
Memory Stick Host Controller (MSHC) Module
Memory Stick Host Controller Operation
DIV [1:0]
1:1
1:0
SCLK (internal)
MS_SCLKO is generated by this SCLK
0:1
0:0
Serial Clock
Divide Ratio
Source
— —
HCLK Divide by 2
HCLK Divide by 4
HCLK Divide by 8
SCLKI Divide by 1
SCLKI Divide by 2
SCLKI Divide by 4
SCLKI Divide by 8
SCLKO Output
Not supported
1/2 HCLK
1/4 HCLK
1/8 HCLK
SCLKI
1/2 SCLKI
1/4 SCLKI
1/8 SCLKI
21-11