Dq [31:0]—Data Bus (Internal); Ma [11:0]—Multiplexed Address Bus; Sdba [4:0], Sdiba [3:0]—Non-Multiplexed Address Bus; Dqm3, Dqm2, Dqm1, Dqm0—Data Qualifier Mask - Motorola DragonBall MC9328MX1 Reference Manual

SDRAM Memory Controller
24.4.4 DQ [31:0]—Data Bus (Internal)
The 32 data lines are used to transfer data between the SDRAM Controller and memory. Data bit 31 is the
most significant bit and bit 0 is the least significant.
24.4.5 MA [11:0]—Multiplexed Address Bus
The multiplexed address bus specifies the SDRAM page and the location within the page targeted by the
current access. The multiplexed address pins are used in conjunction with some of the non-multiplexed
ARM920T processor address signals to comprise the complete SDRAM address. Connections between the
SDRAM Controller and memory vary depending on the SDRAM device density. See Section 24.7.1,
"Address Multiplexing," on page 24-29 and specifically Table 24-21 and Table 24-23 for details on
supported SDRAM configurations.
24.4.6 SDBA [4:0], SDIBA [3:0]—Non-Multiplexed Address Bus
The non-multiplexed address pins specify the SDRAM bank to which the current command is targeted. In
some density or width configurations, these pins also supply the most significant bits of the row address.
Table 24-21 on page 24-45 and Table 24-22 on page 24-46 document which address pins are used for any
given configuration.
24.4.7 DQM3, DQM2, DQM1, DQM0—Data Qualifier Mask
During read cycles, the DQMx pins control the SDRAM data output buffers. DQMx asserted high disables
the output buffers leaving them in a high-impedance state. DQMx asserted low allows the data buffers to
drive normally.
During write cycles, DQMx controls which bytes are written in the SDRAM. DQMx asserted low enables
a write to the corresponding byte, whereas DQMx asserted high leaves the byte unchanged.
DQM3 corresponds to the most significant byte and DQM0 to the least significant. Sixteen bit memories
require only two DQM connections. Memories aligned to the upper data bus (D [31:16]) connect to DQM3
and DQM2, while memories aligned to the lower data bus (D [15:0]) connect to DQM1 and DQM0.
Memory alignment is selected in the SDCTLx Registers.
24.4.8 SDWE—Write Enable
Write enable is part of the three bit command field (RAS and CAS make up the other two bits) used by the
SDRAM. Generally, SDWE will be asserted low if a command transfers data to the memory. A detailed
summary of the supported SDRAM commands is provided in Table 24-51 on page 24-69.
24.4.9 RAS—Row Address Strobe
Row address strobe is also part of the SDRAM command field. It is generally used to indicate an operation
affecting an entire bank or row. When RAS is asserted (low), a new SDRAM row address must be latched.
Table 24-51 on page 24-69 provides details on SDRAM command encoding.
24-6 MC9328MX1 Reference Manual MOTOROLA