Table 20-15 Interrupt Mechanisms - Motorola DragonBall MC9328MX1 Reference Manual

Table 20-14. MMC/SD Interrupt Mask Register Description (Continued)
Name
BUF_READY
Bit 3
END_CMD_RES
Bit 2
WRITE_OP_DONE
Bit 1
DATA_TRAN
Bit 0
Table 20-15 summarizes the interrupt mechanisms used in the MMC/SD module.
STATUS
Int # Register Source Bit
Name (Number)
1 TIME_OUT_READ (0)
2 TIME_OUT_RESP (1)
3 CRC_WRITE_ERR (2)
4 CRC_READ_ERR (3)
5 RESP_CRC_ERR (5)
6 APPL_BUFF_FE (6)
7 APPL_BUFF_FF (7)
MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD)
Description
Buffer Ready—Masks the Application buffer FIFO
ready (full or empty) interrupt.
End Command Response—Masks the end
command response interrupt.
Write Operation Done—Masks the write
operation done interrupt.
Data Transfer Done—Masks the data transfer
done interrupt.
Table 20-15. Interrupt Mechanisms
Generate
Interrupt?
No, alert via the
DATA_TRANS_DONE
bit in the MMC/SD
Status Register
No, alert via the
END_CMD_RESP
bit in the MMC/SD
Status Register
No, alert via the
DATA_TRANS_DONE
bit in the MMC/SD
Status Register
No, alert via the
DATA_TRANS_DONE
bit in the MMC/SD
Status Register
No, alert via the
END_CMD_RESP
bit in the MMC/SD
Status Register
Yes
Yes
0 = Not masked
1 = Masked
0 = Not masked
1 = Masked
0 = Not masked
1 = Masked
0 = Not masked
1 = Masked
INT_MASK Register
Bit Name (Number)
DATA_TRAN (0)
END_CMD_RES (2)
DATA_TRAN (0)
DATA_TRAN (0)
END_CMD_RES (2)
BUF_READY (3)
BUF_READY (3)
Programming Model
Settings
Interrupt/
Status Clear
Method
Clear status by setting
STOP_CLK in
STR_STP_CLK
Clear status by setting
STOP_CLK in
STR_STP_CLK
Clear status by setting
STOP_CLK in
STR_STP_CLK
Clear status by setting
STOP_CLK in
STR_STP_CLK
Clear status by setting
STOP_CLK in
STR_STP_CLK
Clear interrupt by writing
to INT_MASK bit
Clear status by writing to
BUFFER_ACCESS
Clear interrupt by writing
to INT_MASK bit
Clear status by reading
BUFFER_ACCESS
20-27