Mma Mac Fifo Register; Table 17-8 Mma Mac Fifo Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Multimedia Accelerator (MMA)
Table 17-7. MMA MAC Interrupt Mask Register Description (Continued)
Name
FIFO EMPT FIFO Empty Interrupt Mask—Masks the FIFO EMPT interrupt.
Bit 2
FIFO HALF FIFO Half Full Interrupt Mask—Masks the FIFO HALF interrupt.
Bit 1
FIFO FULL FIFO Full Interrupt Mask—Masks the FIFO FULL interrupt.
Bit 0

17.3.1.7 MMA MAC FIFO Register

MMA_MAC_FIFO
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Name
FIFO REGISTER FIFO Read Register—Returns FIFO output.
Bits 31–0
17-12
Description
MMA MAC FIFO Register
28 27 26 25
FIFO REGISTER
r r r r
0 0 0 0
12 11 10 9
FIFO REGISTER
r r r r
0 0 0 0
Table 17-8. MMA MAC FIFO Register Description
MC9328MX1 Reference Manual
0 = Mask on/enable interrupt
1 = Mask off/disable interrupt
0 = Mask on/enable interrupt
1 = Mask off/disable interrupt
0 = Mask on/enable interrupt
1 = Mask off/disable interrupt
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
r r r r r
0 0 0 0 0
0x0000
Description
Settings
Addr
0x00222018
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
r r r r
0 0 0 0
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