Dct/Idct X-Offset Address; Dct/Idct Y-Offset Address; Table 17-30 Dct/Idct X-Offset Address Register Description - Motorola DragonBall MC9328MX1 Reference Manual

17.3.5.7 DCT/iDCT X-Offset Address

MMA_DCTXOFF
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE rw rw rw
0 0 0
RESET
Table 17-30. DCT/iDCT X-Offset Address Register Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
X-OFFSET X Offset—Determines the offset address along the X-direction from the last transformed block. For
Bits 15–0 the first block, the start address is the same as MMA_DCTSRCDATA or MMA_DCTDESDATA. For
the following blocks the start address is [MMA_DCTSRCDATA or MMA_DCTDESDATA] +
(X-OFFSET × N) where N = 1, ...(X-COUNT – 1) along the X-direction.

17.3.5.8 DCT/iDCT Y-Offset Address

MMA_DCTYOFF
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE rw rw rw
0 0 0
RESET
MOTOROLA
DCT/iDCT X-Offset Address
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
X-OFFSET
rw rw rw rw
0 0 0 0
DCT/iDCT Y-Offset Address
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
Y-OFFSET
rw rw rw rw
0 0 0 0
Multimedia Accelerator (MMA)
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
rw rw rw rw rw
0 0 0 0 0
0x0000
Description
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
rw rw rw rw rw
0 0 0 0 0
0x0000
Programming Model
Addr
0x00222418
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
rw rw rw rw
0 0 0 0
Addr
0x0022241C
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
rw rw rw rw
0 0 0 0
17-29