Motorola DragonBall MC9328MX1 Reference Manual page 461

Table 19-12. Panel Configuration Register Description (Continued)
Name
FLMPOL First Line Marker Polarity—Sets the polarity of
Bit 23 the first line marker symbol.
LPPOL Line Pulse Polarity—Sets the polarity of the line
Bit 22 pulse signal.
CLKPOL LCD Shift Clock Polarity—Sets the polarity of
Bit 21 the active edge of the LCD shift clock.
OEPOL Output Enable Polarity—Sets the polarity of the
Bit 20 output enable signal.
SCLKIDLE LSCLK Idle Enable—Enables/Disables LSCLK
Bit 19 when VSYNC is idle in TFT mode.
END_SEL Endian Select—Selects the image download into
Bit 18 memory as big or little endian format.
SWAP_SEL Swap Select—Controls the swap of data in little
Bit 17 endian mode (when END_SEL = 1 this bit has no
effect).
REV_VS Reverse Vertical Scan—Selects the vertical
Bit 16 scan direction as normal or reverse (the image
flips along the x-axis). The SSA register must be
changed accordingly.
ACDSEL ACD Clock Source Select—Selects the clock
Bit 15 source used by the alternative crystal direction
counter.
ACD Alternate Crystal Direction—Toggles the ACD
Bits 14–8 signal once every 1-16 FLM cycles based on the
value specified in this field. The actual number of
FLM cycles between toggles is the programmed
value plus one.
SCLKSEL LSCLK Select—Selects whether to enable or
Bit 7 disable LSCLK in TFT mode when there is no
data output.
SHARP Sharp Panel Enable—Enables/Disables signals
Bit 6 for Sharp HR-TFT 320 x 240 panels.
PCD Pixel Clock Divider—Holds clock divider value.
Bits 5–0 The LCDC_CLK (PerCLK2) is divided by N (PCD
plus one) to yield the pixel clock rate. Values of 1
to 63 will yield N=2 to 64. The pixel clock rate is
faster than LSCLK by a factor equal to the
number of pixels in an output vector.
For passive matrix color panels (COLOR=1,
TFT=0, PBSIZ=11) PCD must be greater than or
equal to 2.
MOTOROLA
Description
LCD Controller
Programming Model
Settings
0 = Active high
1 = Active low
0 = Active high
1 = Active low
0 = Active negative edge of LSCLK (in TFT
mode, active on positive edge of LSCLK)
1 = Active positive edge of LSCLK (in TFT
mode, active on negative edge of LSCLK)
0 = Active high
1 = Active low
0 = Disable LSCLK
1 = Enable LSCLK
0 = Little endian
1 = Big endian
0 = 16 bpp mode
1 = 8 bpp. 4 bpp, 2 bpp, 1 bpp mode
0 = Vertical scan in normal direction
1 = Vertical scan in reverse direction
0 = Use FRM as clock source for ACD count
1 = Use LP/HSYN as clock source for ACD
count
For active mode (TFT=1), this parameter is not
used.
For passive mode (TFT=0), see description.
0 = Disable OE and LSCLK in TFT mode when
no data output
1 = Always enable LSCLK in TFT mode even if
there is no data output
0 = Disable Sharp signals
1 = Enable Sharp signals
The value of PCD must be set such that the
LSCLK frequency is less than or equal to one
fifth of the HCLK frequency, otherwise the LD
will be wrong.
When PCD = O, pixel clock frequency is equal
to LCDC_CLK frequency.
19-23