Figure 24-9 Off-Page Burst Read Timing Diagram (32-Bit Memory); Figure 24-10 On-Page Burst Read Timing Diagram (32-Bit Memory); Figure 24-11 Off-Page Write Followed By On-Page Write Timing Diagram - Motorola DragonBall MC9328MX1 Reference Manual

SDCLK
ADDR
ROW
A
t
RCD
RAS,
CAS,
ACT
SDWE
CSDx
DATA
Figure 24-9. Off-Page Burst Read Timing Diagram (32-Bit Memory)
SDCLK
ADDR
RAS,
CAS,
SDWE
CSDx
DATA
Figure 24-10. On-Page Burst Read Timing Diagram (32-Bit Memory)
SDCLK
ADDR
RAS,
CAS,
SDWE
CSDx
DATA
Figure 24-11. Off-Page Write Followed by On-Page Write Timing Diagram
MOTOROLA
COL
A
CAS Latency = 2
Minimum
READ NOP
COLa
READ NOP NOP NOP NOP NOP NOP NOP NOP READ
CAS Latency
Da1 Da2 Da3 Da4
ROW COLUMN
A
t
RCD
ACT WRIT
DATA
SDRAM Memory Controller
NOP NOP NOP
DATA DATA DATA
A1 A2 A3
COLb
COLUMN
A
WRIT
DATA
A
Operating Modes
COL
READ
DATA
A4
TBST
NOP NOP
CAS Latency
Db1
B
B
24-21
B