Vertical Configuration Register; Table 19-14 Vertical Configuration Register Description - Motorola DragonBall MC9328MX1 Reference Manual

19.4.6 Vertical Configuration Register

The Vertical Configuration Register defines the vertical sync pulse timing.
VCR
BIT 31 30 29
V_WIDTH
TYPE rw rw rw
0 0 0
RESET
BIT 15 14 13
TYPE rw rw rw
0 0 0
RESET
Table 19-14. Vertical Configuration Register Description
Name
V_WIDTH Vertical Sync Pulse Width—Specifies the width, in lines, of the VSYNC pulse for active (TFT =1)
Bits 31–26 mode. For a value of "000001", the vertical sync pulse encompasses one HSYNC pulse. For a
value of "000002", the vertical sync pulse encompasses two HSYNC pulses, and so on. For
passive (TFT=0) mode and non-color mode, see Figure 19-12.
Reserved Reserved—These bits are reserved and should read 0.
Bits 25–16
V_WAIT_1 Wait Between Frames 1—Defines the delay, in lines, between the end of the OE pulse and the
Bits 15–8 beginning of the VSYNC pulse for active (TFT=1) mode. This field has no meaning in passive
non-color mode. The actual delay is (V_WAIT_1). In passive color mode, this field is the delay,
measured in virtual clock periods, between the last line of the frame to the beginning of the next
frame.
V_WAIT_2 Wait Between Frames 2—Defines the delay, in lines, between the end of the VSYNC pulse and
Bits 7–0 the beginning of the OE pulse of the first line in active (TFT=1) mode. The actual delay is
V_WAIT_2 ) lines. Set this field to zero for passive non-color mode. The minimum value of this
field is 0x01.
MOTOROLA
Vertical Configuration Register
28 27 26 25
rw rw rw r
0 0 1 0
12 11 10 9
V_WAIT_1
rw rw rw rw
0 0 0 0
LCD Controller
24 23 22 21 20
r rw rw rw rw
0 0 0 0 0
0x0401
8 7 6 5 4
V_WAIT_2
rw rw rw rw rw
0 0 0 0 0
0x0000
Description
Programming Model
Addr
0x00205020
19 18 17 16
rw rw rw rw
0 0 0 1
3 2 1 0
rw rw rw rw
0 0 0 0
19-25