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MC9328MX1
SSI_TXDAT
SSI_RXDAT
SSI_TXCLK
SSI_TXFS
SYS_CLK
SSI TX/RX Internal Continuous Clock
(RXDIR=0, TXDIR=1, RFDIR=X, TFDIR=1, SYN=1, SYS_CLK_EN=1)
2
SSI I
S Master Mode (I2S_Mode Select=01, SYS_CLK_EN)
MC9328MX1
SSI_TXDAT
SSI_RXDAT
SSI_TXCLK
SSI_TXFS
SSI TX/RX External Continuous Clock
(RXDIR=0, TXDIR=0, RFDIR=X, TFDIR=0, SYN=1)
2
SSI I
S Slave Mode (I2S_Mode Select=10)
Figure 30-15. Synchronous SSI Configurations—Continuous and Gated Clock
An example of the pin signals for an 8-bit data transfer is shown in Figure 30-16. Continuous and gated
clock signals are shown, as well as the bit-length frame sync signal and the word-length frame sync signal.
The shift direction can be defined as MSB first or LSB first.
Continuous SSI_TXCLK, SSI_RXCLK
Gated SSI_TXCLK, SSI_RXCLK
SSI_TXFS, SSI_RXFS
Early SSI_TXFS, SSI_RXFS
SSI_TXDAT
7
6
5
4
3
SSI_RXDAT
7
6
5
4
3
8-Bit Data
MOTOROLA
NOTE:
2
1
0
2
1
0
Figure 30-16. Serial Clock and Frame Sync Timing
Synchronous Serial Interface (SSI)
SSI Data and Control Pins
MC9328MX1
SSI_TXDAT
SSI_RXDAT
SSI_TXCLK
SSI TX/RX Internal Gated Clock
(RXDIR=1, TXDIR=1, SYN=1)
MC9328MX1
SSI_TXDAT
SSI_RXDAT
SSI_TXCLK
SSI TX/RX External Gated Clock
(RXDIR=1, TXDIR=0, SYN=1)
7
6
5
4
3
7
6
5
4
3
Bit Length Frame Sync
Word Length Frame Sync
2
1
0
2
1
0
30-37
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