Register Access During Power Save Mode; Register Access When Mshc Module Is Disabled; Auto Command Function - Motorola DragonBall MC9328MX1 Reference Manual

21.5.5.1 Register Access During Power Save Mode

Note that the following registers cannot be written while the MSHC module is in Power Save Mode (PWS
bit = 1).
• MSCMD, MSTDATA, MSC2 (except MSCEN bit), MSACD, MSFAECS, and MSDRQC register

21.5.5.2 Register Access When MSHC Module is Disabled

The following register must only be written in MSHC module disable mode (MSCEN bit = 0).
• SRC bit and DIV [1:0] bits of MSCLKD register
Setting the MSCEN bit from 1 to 0 causes all of MSHC module's registers to initialize except the MSCEN
bit of MSC2 register and the MSCLKD register.
The following procedure is used to initialize the MSHC module registers for operation:
1. Set the MSCEN bit of MSC2 to
2. Write the value to other registers or other bits of MSC2
3. ...... etc.

21.5.6 Auto Command Function

The MSHC module supports an Auto Command function. Auto Command automatically executes
GET_INT or READ_REG on the host interface for checking status after SET_CMD ends.
With this function, the INT signal from the Memory Stick is detected and the command set in the Memory
Stick Auto Command Register is executed.
The result of an automatically executed command (the value of the read register) is put in the receive data
buffer.
The time required and ARM920T processor load is lower with this function than when the ARM920T
processor executes SET_CMD and then GET_INT (or READ_REG).
Be sure that READ_SIZE is set to 4 half-words or less when executing
READ_REG using the ACD.
Figure 21-5 on page 21-10 indicates the ARM920T core processing and host interface operations when the
ACD is used. This figure illustrates BLOCK_READ in SET_CMD execution.
MOTOROLA
1.
NOTE:
Memory Stick Host Controller (MSHC) Module
Memory Stick Host Controller Operation
21-9