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the physical size constraints of the target applications, the design was optimized for a memory device data
width of 32 bits. Table 24-12 summarizes the devices targeted by the design. The controller is capable of
interfacing with devices of other widths and densities, however, only devices with 4 banks are supported.
A 100 MHz system bus operation is possible with PC100 compliant single data rate memory devices.
Table 24-12. JEDEC Standard Single Data Rate SDRAMs
Item
Bus Width
Depth
Refresh Rows
# Banks
Bank Address
Row Address
Column Address
Data
Qualifiers
24.7.1 Address Multiplexing
The JEDEC standard SDRAMs for which the controller was optimized, use an asymmetrical array
architecture with more row than column address lines. The SDRAM Controller multiplexes only those pins
which change between the row and column addresses. The remaining (most significant) row addresses and
the bank addresses are not multiplexed.
24.7.1.1 Multiplexed Address Bus
The SDRAM Controller multiplexed address bus is aligned to the column addresses so that address line A1
always appears on pin MA0. With this alignment, the "folding point" in the multiplexor is driven solely by
the number of column address bits, although interleave mode causes a two bit shift to account for the bank
addresses. Column bus widths of 8 to 11 bits are supported in non-interleave mode, although only 8 and 9
bit widths are allowed in interleave mode. Table 24-13 summarizes the multiplex options supported by the
controller. Column addresses through A10 are driven regardless of the multiplexor configuration, although
some of the lines will be unused for the smaller page sizes.
Memory width does not affect the multiplexer; however, it does affect how the memories are connected to
the SDRAM Controller pins. The width of the multiplexed bus is one bit larger than in previous
generations of the SDRAMC so that 32-bit memory systems can be supported with a minimal impact on
the multiplex hardware because 32-bit memory systems are shifted left by one bit and use MA [n+1:1].
This is demonstrated in the last two rows of Table 24-13 by the grayed-out boxes. Note that the AP signal
is duplicated in two bit positions to permit this signal to always appear on memory pin A10. Table 24-14
lists the SDRAM interface connections for different configurations of JEDEC SDRAM.
MOTOROLA
64 Mbit
16
32
4 Mword
2 Mword
4096
4096
(15.62 µs)
(15.62 µs)
4
4
2
2
12
11
8
8
2
4
SDRAM Memory Controller
SDRAM Configuration
128 Mbit
16
32
8 Mword
4 Mword
4096
4096
(15.62 µs)
(15.62 µs)
4
4
2
2
12
12
9
8
2
4
General Operation
256 Mbit
16
32
16 Mword
8 Mword
8192
8192
(7.81 µs)
(7.81 µs)
4
4
2
2
13
13
9
8
2
4
24-29
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