Motorola DragonBall MC9328MX1 Reference Manual page 871

Table 30-7. SSI Control/Status Register Description (Continued)
Name
SSI_EN SSI Enable—Enables/Disables the SSI. The SSI Enable bit must
Bit 8 be set prior to setting other bits.
When the SSI is set up for internal frame sync, enabling causes
an output frame sync to be generated. When the SSI is set up for
external frame sync, enabling causes the SSI to wait for the input
frame sync. When the SSI is disabled, the SSI_TXCLK,
SSI_TXFS, and SSI_TXFS pins are tri-stated, the status register
bits hold their reset value, and all internal clocks are disabled
(other than clocking for register access).
Reset the SSI by clearing the SSI_EN bit. The contents of the
transmit FIFO and receive FIFO are cleared when the SSI_EN bit
is reset.
RDR Receive Data Ready—Indicates that the SRX register or the
Bit 7 receive FIFO contains a new value. It is automatically cleared
when the CPU reads the SRX register or when the receive FIFO
(when enabled) is empty.
When the RIE bit in the SRCR is set, an interrupt occurs when the
RDR bit is set.
TDE Transmit Data Register Empty—Indicates that no data is
Bit 6 waiting to be transferred to the TXSR. This occurs when the STX
register is empty. Because the STX register is the first word of the
transmit FIFO, the TDE bit is not set until the transmit FIFO is
empty.
When the TDE bit is set and data is not written to the STX register
or to the SSI Time Slot Register (STSR) before the TXSR
empties, an underrun error occurs.
To clear the TDE bit, write transmission data to the STX register
or write any data to the STSR register.
When the TIE bit in the STCR is set, an interrupt occurs when the
TDE bit is set.
ROE Receive Overrun Error—Indicates when the RXSR is filled and
Bit 5 ready to transfer to the SRX register or the receive FIFO register
(when enabled), and these registers are already full. This is also
indicated by the RFF and Receive Data Ready (RDR) bits of this
register.
When ROE is set, the contents of the RXSR are not transferred.
However, when the ROE bit is set, it causes a change in the
interrupt vector used, allowing the use of a different interrupt
handler for a receive overrun condition. When a receive interrupt
occurs with the ROE bit set, the Receive Data with Exception
interrupt is generated. When a receive interrupt occurs with the
ROE bit cleared, the Receive Data interrupt is generated.
ROE is cleared by reading this register, and then reading the
SRX register.
MOTOROLA
Description
Synchronous Serial Interface (SSI)
Programming Model
Settings
0 = Disable the SSI
1 = Enable the SSI
0 = SRX does not contain a
new value or the receive
FIFO is empty
1 = SRX or receive FIFO
contains a new value
0 = Data is waiting to be
transmitted (transferred
to the TXSR)
1 = No data is waiting to be
transmitted (transferred
to the TXSR)
0 = SRX and/or receive FIFO
can hold more data
1 = RXSR is ready to transfer
data, however SRX
and/or receive FIFO is
full
30-17