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DMA Controller
13.4.3.2 Destination Address Registers
Each of the destination address registers (DARx) contain the destination address for a DMA cycle. The
value of the register remains unchanged throughout the DMA process. If the memory direction bit (MDIR)
in the channel control register (CCR) is clear (indicating a memory address increment), then the
destination address register contains the starting address of the memory block. If MDIR is set (indicating a
memory address decrement), then the destination address register contains the ending address of the
memory block.
DAR0
DAR1
DAR2
DAR3
DAR4
DAR5
DAR6
DAR7
DAR8
DAR9
DAR10
BIT
31
30
29
TYPE
rw
rw
rw
0
0
0
RESET
BIT
15
14
13
TYPE
rw
rw
rw
0
0
0
RESET
Table 13-15. Channel Destination Address Registers Description
Name
DA [31:2]
Destination Address—Contains the destination address to which data is written to during a DMA
Bits 31–2
transfer.
DA [1], DA [0]
Destination Address [1] and Destination Address [0]—To ensure that all addresses are
Bits 1–0
word-aligned, these bits are set internally to 0.
13-20
Channel 0 Destination Address Register
Channel 1 Destination Address Register
Channel 2 Destination Address Register
Channel 3 Destination Address Register
Channel 4 Destination Address Register
Channel 5 Destination Address Register
Channel 6 Destination Address Register
Channel 7 Destination Address Register
Channel 8 Destination Address Register
Channel 9 Destination Address Register
Channel 10 Destination Address Register
28
27
26
25
rw
rw
rw
rw
0
0
0
0
12
11
10
9
DA [15:2]
rw
rw
rw
rw
0
0
0
0
MC9328MX1 Reference Manual
24
23
22
21
DA [31:16]
rw
rw
rw
rw
0
0
0
0
0x0000
8
7
6
5
rw
rw
rw
rw
0
0
0
0
0x0000
Description
Addr
0x00209084
0x002090C4
0x00209104
0x00209144
0x00209184
0x002091C4
0x00209204
0x00209244
0x00209284
0x002092C4
0x00209304
20
19
18
17
rw
rw
rw
rw
0
0
0
0
4
3
2
1
DA [1] DA [0]
rw
rw
rw
rw
0
0
0
0
MOTOROLA
16
rw
0
0
rw
0
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