Motorola DragonBall MC9328MX1 Reference Manual page 849

Name
Reserved Reserved—This bit is reserved and should read 0.
Bit 3
SRW Slave Read/Write—Indicates the value of the R/W
Bit 2 command bit of the I
addressed as a slave (IAAS bit is set). SRW is valid only
when a complete transfer occurs, no other transfers have
been initiated, and the I
address match.
2
IIF I C interrupt—Indicates an interrupt condition. Cleared
Bit 1 by writing 0 in the interrupt routine. Set when one of the
following occurs:
• Completion of one byte transfer (set at the falling
edge of the ninth clock)
• Calling address matches MC9328MX1 slave
address
• Arbitration is lost
RXAK Received Acknowledge—Indicates whether an
Bit 0 acknowledge signal (to the data) was received on SDA.
MOTOROLA
Table 29-7. I2SR Register Description (Continued)
Description
2
C protocol when the device is the
2
C module is a slave with an
2
I C Module
Programming Model
Settings
0 = Slave receiver, master writing to slave
1 = Slave transmitter, master reading from
slave
2
0 = No I C interrupt pending
1 = An interrupt is pending, which causes
a processor interrupt request
(when IIEN = 1).
0 = An acknowledge signal was received
after the completion of 8-bit data
transmission on the bus
1 = No acknowledge signal was detected
at the ninth clock
29-13