Sign In
Upload
Manuals
Brands
Motorola Manuals
Computer Hardware
MC68VZ328
Motorola MC68VZ328 Manuals
Manuals and User Guides for Motorola MC68VZ328. We have
1
Motorola MC68VZ328 manual available for free PDF download: User Manual
Motorola MC68VZ328 User Manual (376 pages)
Motorola MC68VZ328 Integrated Processor User's Manual
Brand:
Motorola
| Category:
Computer Hardware
| Size: 5.3 MB
Table of Contents
Table of Contents
3
List of Figures
15
Audience
27
Organization
27
About this Book
27
Suggested Reading
29
Conventions
29
Definitions, Acronyms, and Abbreviations
30
Chapter 1 Introduction
31
Introduction
31
Features of the MC68VZ328
32
Figure 1-1 MC68VZ328 Block Diagram
32
Cpu
34
CPU Programming Model
35
Figure 1-2 User Programming Model
35
Figure 1-3 Supervisor Programming Model Supplement
35
Data and Address Mode Types
36
FLX68000 Instruction Set
36
Table 1-1 Address Modes
36
Table 1-2 Instruction Set
37
Clock Generation Module and Power Control Module
38
Memory Controller
38
Modules of the MC68VZ328
38
Chip-Select Logic
39
DRAM Controller
39
Interrupt Controller
39
LCD Controller
39
System Control
39
General-Purpose I/O (GPIO) Lines
40
General-Purpose Timer
40
Real-Time Clock
40
Serial Peripheral Interfaces (SPI)
40
Universal Asynchronous Receiver/Transmitter (UART) Modules
40
Bootstrap Mode
41
In-Circuit Emulation Module
41
Pulse-Width Modulators (PWM)
41
Chapter 2 Signal Descriptions
43
Figure 2-1 Signals Grouped by Function
44
Signals Grouped by Function
44
Table 2-1 Signal Function Groups
45
Clock and System Control Signals
46
Figure 2-2 Typical Crystal Connection
46
Power and Ground Signals
46
Address Bus Signals
47
Data Bus Signals
47
Bus Control Signals
48
Interrupt Controller Signals
48
LCD Controller Signals
49
Timer Signals
50
UART 1 and UART 2 Controller Signals
50
Pulse-Width Modulator Signals
51
Serial Peripheral Interface 1 Signals
51
Serial Peripheral Interface 2 Signals
51
Chip-Select and EDO RAM Interface Signals
52
SDRAM Interface Signals
52
In-Circuit Emulation (ICE) Signals
53
Chapter 3 Memory Map
55
Figure 3-1 MC68VZ328 System Memory Map
55
Programmer's Memory Map
56
Table 3-1 Programmer's Memory Map (Sorted by Address)
56
Chapter 4 Clock Generation Module and Power Control Module
69
Introduction to the Clock Generation Module
70
Table 4-1 CGM Clock Signal Distribution
70
CGM Operational Overview
71
Figure 4-1 Clock Generation Module (CGM) Simplified Block Diagram
71
CLK32 Clock Signal
72
Detailed CGM Clock Descriptions
72
Figure 4-2 Example of External Crystal Connection
72
PLLCLK Clock Signal
72
Figure 4-3 Initial Power-Up Sequence Timing
73
PLLCLK Initial Power-Up Sequence
73
PLL Frequency Selection
74
PLLCLK Frequency Selection Programming Example
74
Programming Considerations When Changing Frequencies
75
CGM Programming Model
76
PLL Control Register
76
Table 4-2 PLL Control Register Description
76
Table 4-3 WKSEL Field (PLLCR) Delay Settings
77
Introduction to the Power Control Module
78
PLL Frequency Select Register
78
Table 4-4 PLL Frequency Select Register Settings
78
Burst Mode
79
Doze Mode
79
Normal Mode
79
Operating the PCM
79
Burst Mode Operation
80
CGM Operation During Sleep Mode
80
Sleep Mode
80
Figure 4-4 Power Control Module Block Diagram
81
Figure 4-5 Power Control Operation in Burst Mode
81
Power Control Register
82
Table 4-5 Power Control Register Description
82
Bus Monitors and Watchdog Timers
83
Chapter 5 System Control
83
System Control Operation
83
System Control Register
83
Programming Model
84
Table 5-1 System Control Register Description
84
Peripheral Control Register
86
Table 5-2 Peripheral Control Register Description
86
ID Register
87
Table 5-3 ID Register Description
87
I/O Drive Control Register
88
Table 5-4 I/O Drive Control Register Description
88
Chapter 6 Chip-Select Logic
89
Overview of the CSL
89
Chip-Select Operation
90
Memory Protection
90
Table 6-1 Chip-Select and Memory Types
90
Figure 6-1 Size Selection and Memory Protection for CSB0 and CSB1
91
Programmable Data Bus Size
91
Chip-Select Group Base Address Registers
92
Overlapping Chip-Select Registers
92
Programming Model
92
Table 6-2 Chip-Select Group a Base Address Register Description
92
Table 6-3 Chip-Select Group B Base Address Register Description
93
Table 6-4 Chip-Select Group C Base Address Register Description
93
Chip-Select Upper Group Base Address Register
94
Table 6-5 Chip-Select Group D Base Address Register Description
94
Table 6-6 Chip-Select Upper Group Base Address Register Description
94
Chip-Select Registers
96
Table 6-7 Chip-Select Register a Description
96
Table 6-8 Chip-Select Register B Description
98
Table 6-9 Chip-Select Register C Description
100
Table 6-10 Chip-Select Register D Description
102
Chip-Select Control Register 1
104
Emulation Chip-Select Register
104
Table 6-11 Emulation Chip-Select Register Description
104
Table 6-12 Chip-Select Control Register 1 Description
105
Chip-Select Control Register 2
106
Table 6-13 Chip-Select Control Register 2 Description
106
Chip-Select Control Register 3
108
Table 6-14 Chip-Select Control Register 3 Description
108
Chapter 7 DRAM Controller
111
Introduction to the DRAM Controller
111
Figure 7-1 DRAM Controller Block Diagram
112
Address Multiplexing
113
DRAM Controller Operation
113
Table 7-1 DRAM Address Multiplexing Options
114
Table 7-2. 16 Mbit SDRAM-256 (16-Bit) and 512 (8-Bit) Page Size
115
Table 7-3. 64 Mbit SDRAM-256 (16-Bit) and 512 (8-Bit) Page Size
115
Table 7-4. 128 Mbit SDRAM-512 (16-Bit) and 1024 (8-Bit) Page Size
116
Table 7-5. 256 Mbit SDRAM-512 (16-Bit) and 1024 (8-Bit) Page Size
116
DTACK Generation
117
Refresh Control
117
Figure 7-2 LCD Controller and DRAM Controller Interface
118
LCD Interface
118
8-Bit Mode
119
Low-Power Standby Mode
119
Data Retention During Reset
120
Figure 7-3 Data Retention for the Reset Cycle
120
Data Retention Sequence
121
DRAM Memory Configuration Register
122
Programming Model
122
Table 7-6 DRAM Memory Configuration Register Description
122
DRAM Control Register
124
Table 7-7 DRAM Control Register Description
124
SDRAM Control Register
126
Table 7-8 SDRAM Control Register Description
126
Table 7-9 SDRAM Bank Address Programming Examples
127
SDRAM Power-Down Register
128
Table 7-10 SDRAM Power-Down Register Description
128
Chapter 8 LCD Controller
129
LCD Controller Features
129
Figure 8-1 LCD Controller Block Diagram
130
LCD Controller Operation
130
Connecting the LCD Controller to an LCD Panel
131
Panel Interface Timing
131
Controlling the Display
132
Figure 8-2 LCD Interface Timing for 4-, 2-, and 1-Bit Data Widths
132
Format of the LCD Screen
132
Figure 8-3 LCD Screen Format
133
Format of the Cursor
133
Figure 8-4 Mapping Memory Data on the Screen
134
Generating Grayscale Tones
134
Mapping the Display Data
134
Table 8-1 Grey Palette Density
135
Bus Bandwidth Calculation Example
136
Using Low-Power Mode
136
Using the DMA Controller
136
Canceling Self-Refresh Mode
137
Entering Self-Refresh Mode
137
Self-Refresh Mode
137
LCD Screen Starting Address Register
138
Programming Model
138
Table 8-2 LCD Screen Starting Address Register Description
138
LCD Screen Width Register
139
LCD Virtual Page Width Register
139
Table 8-3 LCD Virtual Page Width Register Description
139
Table 8-4 LCD Screen Width Register Description
139
LCD Cursor X Position Register
140
LCD Screen Height Register
140
Table 8-5 LCD Screen Height Register Description
140
Table 8-6 LCD Cursor X Position Register Description
140
LCD Cursor y Position Register
141
Table 8-7 LCD Cursor y Position Register Description
141
LCD Blink Control Register
142
LCD Cursor Width and Height Register
142
Table 8-8 LCD Cursor Width and Height Register Description
142
LCD Panel Interface Configuration Register
143
Table 8-10 LCD Panel Interface Configuration Register Description
143
Table 8-9 LCD Blink Control Register Description
143
LACD Rate Control Register
144
LCD Polarity Configuration Register
144
Table 8-11 LCD Polarity Configuration Register Description
144
LCD Pixel Clock Divider Register
145
Table 8-12 LACD Rate Control Register Description
145
Table 8-13 LCD Pixel Clock Divider Register Description
145
LCD Clocking Control Register
146
LCD Refresh Rate Adjustment Register
146
Table 8-14 LCD Clocking Control Register Description
146
Table 8-15 LCD Refresh Rate Adjustment Register Description
146
LCD Frame Rate Control Modulation Register
147
LCD Panning Offset Register
147
Table 8-16 LCD Panning Offset Register Description
147
LCD Gray Palette Mapping Register
148
PWM Contrast Control Register
148
Table 8-17 LCD Gray Palette Mapping Register Description
148
Table 8-18 PWM Contrast Control Register Description
148
Refresh Mode Control Register
149
Table 8-19 Refresh Mode Control Register Description
149
DMA Control Register
150
Programming Example
150
Table 8-20 DMA Control Register Description
150
Chapter 9 Interrupt Controller
151
Figure 9-1 Interrupt Processing Flowchart
152
Interrupt Processing
152
Exception Vectors
153
Table 9-1 Exception Vector Assignment
153
Reset
154
Data Bus Width for Boot Device Operation
155
Interrupt Controller Operation
155
Interrupt Priority Processing
155
Operation Mode Selection During Reset
155
Interrupt Vector Register
156
Interrupt Vectors
156
Table 9-2 Interrupt Vector Numbers
156
Vector Generation
156
Table 9-3 Interrupt Vector Register Description
157
Interrupt Control Register
158
Table 9-4 Interrupt Control Register Description
158
Interrupt Mask Register
160
Table 9-5 Interrupt Mask Register Description
160
Interrupt Status Register
162
Table 9-6 Interrupt Status Register Description
162
Interrupt Pending Register
166
Table 9-7 Interrupt Pending Register Description
166
Interrupt Level Register
169
Table 9-8 Interrupt Level Register Field Values
169
Keyboard Interrupts
170
Pen Interrupts
170
Chapter 10 I/O Ports
171
Port Configuration
171
Status of I/O Ports During Reset
172
Table 10-1 Dedicated I/O Functions of Ports
172
Warm Reset
172
Figure 10-1 I/O Port Warm Reset Timing
173
Power-Up Reset
173
Data Flow from the I/O Module
174
I/O Port Operation
174
Summary of Port Behavior During Reset
174
Table 10-2 MC68VZ328 I/O Port Status During the Reset Assertion Time Length
174
Data Flow to the I/O Module
175
Figure 10-2 I/O Port Operation
175
Operating a Port as GPIO
175
Port a Registers
176
Port Pull-Up and Pull-Down Resistors
176
Programming Model
176
Table 10-3 Pull-Up and Pull-Down Resistors by Port
176
Port a Data Register
177
Port a Direction Register
177
Table 10-4 Port a Direction Register Description
177
Table 10-5 Port a Data Register Description
177
Port a Pull-Up Enable Register
178
Port B Direction Register
178
Port B Registers
178
Table 10-6 Port a Pull-Up Enable Register Description
178
Port B Data Register
179
Table 10-7 Port B Direction Register Description
179
Table 10-8 Port B Data Register Description
179
Port B Dedicated I/O Functions
180
Port B Pull-Up Enable Register
180
Table 10-9 Port B Dedicated Function Assignments
180
Port B Select Register
181
Port C Registers
181
Table 10-10 Port B Pull-Up Enable Register Description
181
Table 10-11 Port B Select Register Description
181
Port C Data Register
182
Port C Direction Register
182
Table 10-12 Port C Direction Register Description
182
Table 10-13 Port C Data Register Description
182
Port C Dedicated I/O Functions
183
Port C Pull-Down Enable Register
183
Table 10-14 Port C Dedicated Function Assignments
183
Table 10-15 Port C Pull-Down Enable Register Description
183
Port C Select Register
184
Table 10-16 Port C Select Register Description
184
Figure 10-3 Interrupt Port Operation
185
Port D Operation
185
Port D Direction Register
186
Port D Registers
186
Table 10-17 Port D Direction Register Description
186
Port D Data Register
187
Table 10-18 Port D Data Register Description
187
Table 10-19 Port D Dedicated Function Assignments
187
Port D Interrupt Options
188
Port D Pull-Up Enable Register
188
Table 10-20 Port D Pull-Up Enable Register Description
188
Port D Polarity Register
189
Port D Select Register
189
Table 10-21 Port D Select Register Description
189
Table 10-22 Port D Polarity Register Description
189
Port D Interrupt Request Edge Register
190
Port D Interrupt Request Enable Register
190
Port D Keyboard Enable Register
190
Table 10-23 Port D Interrupt Request Enable Register Description
190
Table 10-24 Port D Keyboard Enable Register Description
190
Port E Direction Register
191
Port E Registers
191
Table 10-25 Port D Interrupt Request Edge Register Description
191
Table 10-26 Port E Direction Register Description
191
Port E Dedicated I/O Functions
192
Table 10-27 Port E Data Register Description
192
Table 10-28 Port E Dedicated Function Assignments
192
Port E Pull-Up Enable Register
193
Port E Select Register
193
Table 10-29 Port E Pull-Up Enable Register Description
193
Table 10-30 Port E Select Register Description
193
Port F Direction Register
194
Port F Registers
194
Table 10-31 Port F Direction Register Description
194
Port F Data Register
195
Table 10-32 Port F Data Register Description
195
Port F Dedicated I/O Functions
196
Table 10-33 Port F Dedicated I/O Function Assignments
196
Port F Pull-Up/Pull-Down Enable Register
197
Port F Select Register
197
Table 10-34 Port F Pull-Up/Pull-Down Enable Register Description
197
Table 10-35 Port F Select Register Description
197
Port G Data Register
198
Port G Direction Register
198
Port G Registers
198
Table 10-36 Port G Direction Register Description
198
Port G Dedicated I/O Functions
199
Table 10-37 Port G Data Register Description
199
Table 10-38 Port G Dedicated I/O Function Assignments
199
Port G Operational Considerations
200
Port G Pull-Up Enable Register
200
Port G Select Register
200
Table 10-39 Port G Pull-Up Enable Register Description
200
Port J Direction Register
201
Port J Registers
201
Table 10-40 Port G Select Register Description
201
Table 10-41 Port J Direction Register Description
201
Port J Data Register
202
Port J Dedicated I/O Functions
202
Table 10-42 Port J Data Register Description
202
Table 10-43 Port J Dedicated I/O Function Assignments
202
Port J Pull-Up Enable Register
203
Port J Select Register
203
Table 10-44 Port J Pull-Up Enable Register Description
203
Table 10-45 Port J Select Register Description
203
Port K Data Register
204
Port K Direction Register
204
Port K Registers
204
Table 10-46 Port K Direction Register Description
204
Port K Dedicated I/O Functions
205
Table 10-47 Port K Data Register Description
205
Table 10-48 Port K Dedicated I/O Function Assignments
205
Port K Pull-Up/Pull-Down Enable Register
206
Port K Select Register
206
Table 10-49 Port K Pull-Up/Pull-Down Enable Register Description
206
Table 10-50 Port K Select Register Description
206
Port M Direction Register
207
Port M Registers
207
Table 10-51 Port M Direction Register Description
207
Port M Data Register
208
Table 10-52 Port M Data Register Description
208
Port M Dedicated I/O Functions
209
Port M Pull-Up/Pull-Down Enable Register
209
Table 10-53 Port M Dedicated I/O Function Assignments
209
Table 10-54 Port M Pull-Up/Pull-Down Enable Register Description
209
Port M Select Register
210
Table 10-55 Port M Select Register Description
210
Chapter 11 Real-Time Clock
211
Figure 11-1 Real-Time Clock Module Simplified Block Diagram
211
Prescaler
212
RTC Overview
212
Table 11-1 RTC Interrupt Mapping
212
Alarm
213
Time-Of-Day Counter
213
Minute Stopwatch
214
MC68VZ328 User's Manual
214
Minute Stopwatch Application Example
214
Real-Time Interrupt Timer
214
Watchdog Timer
214
Programming Model
215
RTC Time Register
215
Table 11-2 RTC Hours, Minutes, and Seconds Register Description
215
RTC Day Count Register
216
Table 11-3 RTC Day Counter Register Description
216
RTC Alarm Register
217
Table 11-4 RTC Alarm Register Description
217
RTC Day Alarm Register
218
Table 11-5 RTC Day Alarm Register Description
218
Table 11-6 Watchdog Timer Register Description
219
Watchdog Timer Register
219
RTC Control Register
220
RTC Interrupt Status Register
220
Table 11-7 RTC Control Register Description
220
Table 11-8 RTC Interrupt Status Register Description
221
RTC Interrupt Enable Register
222
Table 11-9 Real-Time Interrupt Frequency Settings
222
Table 11-10 RTC Interrupt Enable Register Description
223
Stopwatch Minutes Register
224
Table 11-11 Stopwatch Minutes Register Description
224
Chapter 12 General-Purpose Timers
225
Figure 12-1 General-Purpose Timer Block Diagram
225
GP Timer Overview
225
Clock Source and Prescaler
226
Free-Running Mode
226
Restart Mode
226
Timer Events and Modes of Operation
226
Timer Capture Register
227
TOUT/TIN/PB6 Pin
227
Cascaded Timers
228
Compare and Capture Using Cascaded Timers
228
Table 12-1 Cascade Timer Settings
228
Figure 12-2 Compare Routine for 32-Bit Cascaded Timers
229
Programming Model
230
Table 12-2 Timer Control Register Description
230
Timer Control Registers 1 and 2
230
Table 12-3 Timer Prescaler Register Description
232
Timer Prescaler Registers 1 and 2
232
Table 12-4 Timer Compare Register Description
233
Timer Compare Registers 1 and 2
233
Table 12-5 Timer Capture Register Description
234
Timer Capture Registers 1 and 2
234
Table 12-6 Timer Counter Register Description
235
Timer Counter Registers 1 and 2
235
Table 12-7 Timer Status Register Description
236
Timer Status Registers 1 and 2
236
Chapter 13 Serial Peripheral Interface 1 and 2
237
Figure 13-1 SPI 1 Block Diagram
237
SPI 1 Overview
237
Figure 13-2 SPI 1 Generic Timing
238
SPI 1 Operation
238
Using SPI 1 as Master
238
Using SPI 1 as Slave
238
SPI 1 Phase and Polarity Configurations
239
SPI 1 Signals
239
SPI 1 Programming Model
240
SPI 1 Receive Data Register
240
Table 13-1 SPI 1 Receive Data Register Description
240
SPI 1 Transmit Data Register
241
Table 13-2 SPI 1 Transmit Data Register Description
241
SPI 1 Control/Status Register
242
Table 13-3 SPI 1 Control/Status Register Description
242
SPI 1 Interrupt Control/Status Register
244
Table 13-4 SPI 1 Interrupt Control/Status Register Description
244
SPI 1 Sample Period Control Register
246
SPI 1 Test Register
246
Table 13-5 SPI 1 Test Register Description
246
Figure 13-3 SPI 2 Block Diagram
247
SPI 2 Overview
247
Table 13-6 SPI 1 Sample Period Control Register Description
247
Figure 13-4 SPI 2 Generic Timing
248
SPI 2 Operation
248
SPI 2 Phase and Polarity Configurations
249
SPI 2 Signals
249
SPI 2 Data Register
250
SPI 2 Data Register Timing
250
SPI 2 Programming Model
250
Table 13-7 SPI 2 Data Register Description
250
SPI 2 Control/Status Register
251
Table 13-8 SPI 2 Control/Status Register Description
251
Chapter 14 Universal Asynchronous Receiver/Transmitter 1 and
253
Introduction to the Uarts
253
Figure 14-1 UART Simplified Block Diagram
254
NRZ Mode
254
Serial Operation
254
Figure 14-2 NRZ ASCII "A" Character with Odd Parity
255
Figure 14-3 Irda ASCII "A" Character with Odd Parity
255
Irda Mode
255
Serial Interface Signals
255
Transmitter Operation
256
Txfifo Buffer Operation
256
UART Operation
256
CTS Signal Operation
257
Baud Rate Generator Operation
258
Receiver Operation
258
Rx FIFO Buffer Operation
258
Divider
259
Figure 14-4 Baud Rate Generator Block Diagram
259
Non-Integer Prescaler
259
Table 14-1 Non-Integer Prescaler Values
260
Table 14-2 Non-Integer Prescaler Settings
260
Integer Prescaler
261
Table 14-3 Selected Baud Rate Settings
261
Programming Model
262
Table 14-4 UART 1 Status/Control Register Description
262
UART 1 Status/Control Register
262
Table 14-5 UART 1 Baud Control Register Description
264
UART 1 Baud Control Register
264
Table 14-6 UART 1 Receiver Register Description
265
UART 1 Receiver Register
265
Table 14-7 UART 1 Transmitter Register Description
266
UART 1 Transmitter Register
266
Table 14-8 UART 1 Miscellaneous Register Description
268
UART 1 Miscellaneous Register
268
Table 14-9 UART 1 Non-Integer Prescaler Register Description
270
UART 1 Non-Integer Prescaler Register
270
Non-Integer Prescaler Programming Example
271
Table 14-10 UART 2 Status/Control Register Description
272
UART 2 Status/Control Register
272
Table 14-11 UART 2 Baud Control Register Description
274
UART 2 Baud Control Register
274
Table 14-12 UART 2 Receiver Register Description
275
UART 2 Receiver Register
275
Table 14-13 UART 2 Transmitter Register Description
276
UART 2 Transmitter Register
276
Table 14-14 UART 2 Miscellaneous Register Description
278
UART 2 Miscellaneous Register
278
Table 14-15 UART 2 Non-Integer Prescaler Register Description
280
UART 2 Non-Integer Prescaler Register
280
FIFO Level Marker Interrupt Register
281
Table 14-16 FIFO Level Marker Interrupt Register Description
281
Table 14-17 FIFO Level Marker Settings
282
Chapter 15 Pulse-Width Modulator 1 and 2
283
Figure 15-1 PWM 1 and PWM 2 System Configuration Diagram
283
Introduction to PWM Operation
283
Figure 15-2 PWM 1 Block Diagram
284
PWM Clock Signals
284
D/A Mode
285
Figure 15-3 Audio Waveform Generation
285
Playback Mode
285
PWM Operation
285
Tone Mode
285
Programming Model
286
PWM 1 Control Register
286
Table 15-1 PWM 1 Control Register Description
286
PWM 1 Sample Register
288
Table 15-2 PWM 1 Sample Register Description
288
PWM 1 Counter Register
289
PWM 1 Period Register
289
Table 15-3 PWM 1 Period Register Description
289
Table 15-4 PWM 1 Counter Register Description
289
Figure 15-4 PWM 2 Block Diagram
290
Pwm 2
290
PWM 2 Control Register
290
Table 15-5 PWM 2 Control Register Description
290
PWM 2 Period Register
291
Table 15-6 PWM 2 Period Register Description
291
PWM 2 Counter Register
292
PWM 2 Pulse Width Register
292
Table 15-7 PWM 2 Pulse Width Control Register Description
292
Table 15-8 PWM 2 Counter Register Description
292
Chapter 16 In-Circuit Emulation
293
Figure 16-1 In-Circuit Emulation Module Block Diagram
293
Detecting Breakpoints
294
Entering Emulation Mode
294
ICE Operation
294
Execution Breakpoints Vs. Bus Breakpoints
295
Using the A-Line Insertion Unit
295
Using the Interrupt Gate Module
295
Using the Signal Decoder
295
In-Circuit Emulation Module Address Compare and Mask Registers
296
Programming Model
296
Table 16-1 ICE Module Address Compare and Mask Registers Description
297
In-Circuit Emulation Module Control Compare and Mask Register
298
Table 16-2 ICE Module Control Compare Register Description
298
Table 16-3 ICE Control Mask Register Description
298
In-Circuit Emulation Module Control Register
300
Table 16-4 ICE Module Control Register Description
300
Table 16-5 Emulation Mode Hard Coded Memory Locations
301
In-Circuit Emulation Module Status Register
302
Table 16-6 ICE Module Status Register Description
302
Typical Design Programming Example
302
Dedicated Debug Monitor Memory
303
Figure 16-2 Typical Emulator Design Example
303
Host Interface
303
Emulation Memory Mapping FPGA and Emulation Memory
304
Optional Extra Hardware Breakpoint
304
Optional Trace Module
304
Plug-In Emulator Design Example
304
Figure 16-3 Plug-In Emulator Design Example
305
Application Development Design Example
306
Figure 16-4 Application Development System Design Example
306
Bootstrap Mode Operation
307
Chapter 17 Bootstrap Mode
307
Bootstrap Record Format
308
Data B-Record Format
308
Entering Bootstrap Mode
308
Execution B-Record Format
308
Figure 17-1 Bootstrap Mode Reset Timing
308
Table 17-1 Bootstrap Record Format
308
Changing the Speed of Communication
309
Setting up the RS-232 Terminal
309
System Initialization Programming Example
310
Application Programming Example
311
Bootloader Flowchart
312
Example of Instruction Buffer Usage
312
Figure 17-2 Bootloader Program Operation
313
Special Notes
314
8-Bit Bus Width Issues
315
Chapter 18 Application Guide
315
Design Checklist
315
Determining the Chip ID and Version
315
Bus and I/O Considerations
316
Clock and Layout Considerations
316
Chapter 19 Electrical Characteristics
317
Maximum Ratings
317
Table 19-1 Maximum Ratings
317
AC Electrical Characteristics
318
CLKO Reference to Chip-Select Signals Timing
318
DC Electrical Characteristics
318
Table 19-2 Maximum and Minimum DC Characteristics
318
Chip-Select Read Cycle Timing
319
Figure 19-1 CLKO Reference to Chip-Select Signals Timing Diagram
319
Table 19-3 CLKO Reference to Chip-Select Signals Timing Parameters
319
Figure 19-2 Chip-Select Read Cycle Timing Diagram
320
Table 19-4 Chip-Select Read Cycle Timing Parameters
320
Chip-Select Write Cycle Timing
321
Figure 19-3 Chip-Select Write Cycle Timing Diagram
321
Chip-Select Flash Write Cycle Timing
322
Table 19-5 Chip-Select Write Cycle Timing Parameters
322
Figure 19-4 Chip-Select Flash Write Cycle Timing Diagram
323
Table 19-6 Chip-Select Flash Write Cycle Timing Parameters
323
Chip-Select Timing Trim
324
DRAM Read Cycle 16-Bit Access (CPU Bus Master)
324
Figure 19-5 Chip-Select Timing Trim Timing Diagram
324
Table 19-7 Chip-Select Timing Trim Timing Parameters
324
Figure 19-6 DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Diagram
325
Table 19-8 DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Parameters
325
DRAM Write Cycle 16-Bit Access (CPU Bus Master)
326
Figure 19-7 DRAM Write Cycle 16-Bit Access (CPU Bus Master) Timing Diagram
326
DRAM Hidden Refresh Cycle (Normal Mode)
327
Table 19-9 DRAM Write Cycle 16-Bit Access (CPU Bus Master) Timing Parameters
327
DRAM Hidden Refresh Cycle (Low-Power Mode)
328
Figure 19-8 DRAM Hidden Refresh Cycle (Normal Mode) Timing Diagram
328
Figure 19-9 DRAM Hidden Refresh Cycle (Low-Power Mode) Timing Diagram
328
Table 19-10 DRAM Hidden Refresh Cycle (Normal Mode) Timing Parameters
328
Figure 19-10 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access Timing Diagram
329
LCD SRAM/ROM DMA Cycle 16-Bit Mode Access (1 Wait State)
329
Table 19-11 DRAM Hidden Refresh Cycle (Low-Power Mode) Timing Parameters
329
Figure 19-11 LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master)
330
LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master)
330
Table 19-12 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access Timing Parameters
330
Table 19-13 LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master)
331
Figure 19-12 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)
332
LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)
332
Table 19-14 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)
332
Figure 19-13 LCD Controller Timing Diagram (Normal Mode)
333
LCD Controller Timing
333
Figure 19-14 LCD Controller Timing Diagram (Self-Refresh Mode)
334
Table 19-15 LCD Controller Timing Parameters
334
Page-Miss SDRAM CPU Read Cycle (CAS Latency = 1)
335
Figure 19-15 Page-Miss SDRAM CPU Read Cycle Timing Diagram
335
MC68VZ328 User's Manual
336
Figure 19-16 Page-Hit SDRAM CPU Read Cycle Timing Diagram
336
Page-Hit SDRAM CPU Read Cycle (CAS Latency = 1)
336
Figure 19-17 Page-Hit CPU Read Cycle for 8-Bit SDRAM Timing Diagram
337
Page-Hit CPU Read Cycle for 8-Bit SDRAM (CAS Latency = 1)
337
Figure 19-18 Page-Miss SDRAM CPU Write Cycle Timing Diagram
338
Page-Miss SDRAM CPU Write Cycle (CAS Latency = 1)
338
Figure 19-19 Page-Hit SDRAM CPU Write Cycle Timing Diagram
339
Page-Hit SDRAM CPU Write Cycle (CAS Latency = 1)
339
Figure 19-20 Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM Timing Diagram
340
Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM (CAS Latency = 1)
340
Figure 19-21 Page-Hit CPU Read Cycle in Power-Down Mode Timing Diagram
341
Page-Hit CPU Read Cycle in Power-Down Mode (CAS Latency = 1, Bit APEN of SDRAM Power-Down Register = 1)
341
Exit Self-Refresh Due to CPU Read Cycle (CAS Latency = 1, Bit RM of DRAM Control Register = 1)
342
Figure 19-22 Exit Self-Refresh Due to CPU Read Cycle Timing Diagram
342
Enter Self-Refresh Due to no Activity for 64 Clocks
343
Register = 1)
343
Figure 19-23 Enter Self-Refresh Due to no Activity Timing Diagram
343
Figure 19-24 Page-Miss at Starting of LCD DMA for SDRAM Timing Diagram
344
MC68VZ328 User's Manual
344
Page-Miss at Starting of LCD DMA for SDRAM (CAS Latency = 1)
344
Figure 19-25 Page-Miss at Start and in Middle of LCD DMA Timing Diagram
345
Page-Miss at Start and in Middle of LCD DMA (CAS Latency = 1)
345
Figure 19-26 Page-Hit LCD DMA Cycle for SDRAM Timing Diagram
346
Page-Hit LCD DMA Cycle for SDRAM (CAS Latency = 1)
346
Figure 19-27 SPI 1 and SPI 2 Generic Timing Diagram
348
Figure 19-28 SPI 1 Master Using DATA_READY Edge Trigger Timing Diagram
348
SPI 1 and SPI 2 Generic Timing
348
SPI 1 Master Using DATA_READY Edge Trigger
348
Figure 19-29 SPI 1 Master Using DATA_READY Level Trigger Timing Diagram
349
Figure 19-30 SPI 1 Master "Don't Care" DATA_READY Timing Diagram
349
Figure 19-31 SPI 1 Slave FIFO Advanced by Bit Count Timing Diagram
349
SPI 1 Master "Don't Care" DATA_READY
349
SPI 1 Master Using DATA_READY Level Trigger
349
SPI 1 Slave FIFO Advanced by Bit Count
349
Figure 19-32 SPI 1 Slave FIFO Advanced by SS Rising Edge Timing Diagram
350
SPI 1 Slave FIFO Advanced by SS Rising Edge
350
Emulation Mode Timing
351
Figure 19-33 Normal Mode Timing Diagram
351
Figure 19-34 Emulation Mode Timing Diagram
351
Normal Mode Timing
351
Bootstrap Mode Timing
352
Figure 19-35 Bootstrap Mode Timing Diagram
352
Chapter 20 Mechanical Data and Ordering Information
353
Ordering Information
353
Table 20-1 MC68VZ328 Ordering Information
353
Figure 20-1 MC68VZ328 TQFP Pin Assignments-Top View
354
TQFP Pin Assignments
354
Figure 20-2 MC68VZ328 TQFP Mechanical Drawing
355
TQFP Package Dimensions
355
Figure 20-3 MC68VZ328 MAPBGA Pin Assignments-Top View
356
MAPBGA Pin Assignments
356
Figure 20-4 MC68VZ328 MAPBGA Mechanical Drawing
357
MAPBGA Package Dimensions
357
PCB Finish Requirement
358
Advertisement
Advertisement
Related Products
Motorola MC68306
Motorola MC68302
Motorola DragonBall MC68328
Motorola MC68EC000
Motorola MC68010
Motorola MC6805R Series
Motorola MC6805U2
Motorola MC6805R3
Motorola MC68EC060
Motorola MC68LC060
Motorola Categories
Cell Phone
Two-Way Radio
Baby Monitor
Cordless Telephone
Radio
More Motorola Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL