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Universal Asynchronous Receiver/Transmitters (UART) Modules
There is also a transmitter register (UTXD_1/UTXD_2) and a receiver register (URXD_1/URXD_2). The
registers are optimized for a 32-bit bus. All status bits associated with the received data are accessible
along with the data in a single read. Except for the transmit data (TX_DATA) field in the UART
Transmitter Registers, all register bits are readable and most are read/write. The UART Baud Rate Count
Register (UBRC_1/UBRC_2) performs automatic baud rate detection. There are also two registers for the
escape sequence detection, the UART Escape Character Register (UESC_1/UESC_2) and the UART
Escape Timer Register (UTIM_1/UTIM_2). The following sections describe the basic functionality of the
major blocks in UART module.
The MC9328MX1 only supports a 16 MHz reference frequency. The reference frequency is defined as the
input peripheral clock, PERCLK1, divided by the value of the RFDIV [2:0] bits in the UFCR. Also note
that the frequency of the system/CPU clock (HCLK/BCLK) must be greater than the UART reference
frequency. For example, if the UART reference frequency is 16 MHz, BCLK must be greater than
16 MHz. If the BCLK frequency is not greater, some of the UART features may not operate properly. For
more details on BLCK please refer to Chapter 12, "Phase-Locked Loop and Clock Controller."
27.5.1 Transmitter
The transmitter accepts a parallel character from the ARM920T processor and transmits it serially. The
start, stop, and parity (when enabled) bits are added to the character. When the ignore RTS bit (IRTS) is
set, the transmitter sends a character as soon as it is ready to transmit. RTS can be used to provide
flow-control of the serial data. When RTS is negated (high), the transmitter finishes sending the character
in progress (if any), stops, and waits for RTS to be asserted (low) again. Generation of BREAK characters
and parity errors (for debugging purposes) is supported. The transmitter operates from the 1x clock
provided by the BRM. Normal NRZ encoded data is transmitted when the IR interface is disabled.
The transmitter FIFO (TxFIFO) contains 32 bytes. The data is written to TxFIFO by writing to the
UTXnD_1/UTXnD_2 register with the byte data to the [7:0] bits. The TxFIFO is addressed using the
UTXnD_1/UTXnD_2 register with any one of the 16 addresses (0x00212040
written consecutively if the TxFIFO is not full or is read consecutively if the TxFIFO is not empty. If the
TxFIFO is full and data is again attempted to be written to the FIFO, the overrun bit will be set and data
cannot be written unless a read is first performed.
27.5.2 Transmitter FIFO Empty Interrupt Suppression
The transmitter FIFO empty interrupt suppression logic suppresses the interrupt between writes to the
TxFIFO. When a character is written to the TxFIFO, it is immediately transferred to the transmitter shift
register (PISO_OUT) on the next transmit baud rate clock (when the transmitter is enabled). The
suppression logic allows the software to write another character to the TxFIFO before the interrupt is
asserted. When the transmitter shift register empties before another character is written to the TxFIFO, the
interrupt is asserted. Writing data (even a single character) to the TxFIFO releases the interrupt. The
interrupt is asserted on the following conditions:
•
System Reset
•
UART module reset
•
When a single character has been written to Transmitter FIFO and then the Transmitter FIFO and
the Transmitter Shift Register become empty until another character is written to the Transmitter
FIFO
•
The last character in the TxFIFO is transferred to the shift register, when TxFIFO contains two or
more characters. See Figure 27-3 on page 27-11.
27-10
MC9328MX1 Reference Manual
0x0021207C) and the data is
–
MOTOROLA
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