Ssi_Txfs, Serial Transmit Frame Sync; Ssi_Rxfs, Serial Receive Frame Sync; Figure 30-14 Asynchronous (Syn = 0) Ssi Configurations-Continuous Clock - Motorola DragonBall MC9328MX1 Reference Manual

Synchronous Serial Interface (SSI)

30.4.5 SSI_TXFS, Serial Transmit Frame Sync

The SSI_TXFS pin can be used as either an input or an output. The frame sync is used by the transmitter to
synchronize the transfer of data. The frame sync signal can be 1 bit-clock or 1 word in length and can occur
one bit before the transfer of data or with the transfer of data. (These configurations are set in the STCR.)
In synchronous mode, this pin is used by both the transmit and receive sections. In gated clock mode,
frame sync signals are not used. When SSI_TXFS is configured as input, the external device should drive
SSI_TXFS at the rising or falling edge of SSI_TXCLK, depending on the setting of the TSCKP bit of the
SSI Transmit Configuration Register. SSI_TXFS should sync with the rising edge of SSI_TXCLK if the
data is clocking out at the rising edge of SSI_TXCLK. SSI_TXFS should sync with the falling edge of
SSI_TXCLK if the data is clocking out at the falling edge of SSI_TXCLK.

30.4.6 SSI_RXFS, Serial Receive Frame Sync

The SSI_RXFS pin can be used as either an input or an output. The frame sync is used by the receiver to
synchronize the transfer of data. The frame sync signal can be 1 bit-clock or 1 word in length and can occur
one bit before the transfer of data or with the transfer of data. (These configurations are set in the SRCR.)
When SSI_RXFS is configured as an input, the external device can drive SSI_RXFS at the rising or falling
edge of SSI_RXCLK, depending on the setting of the RSCKP bit of the SRCR Register. SSI_RXFS should
sync with the rising edge of SSI_RXCLK if the data is clocking out at the rising edge of SSI_RXCLK.
SSI_RXFS should sync with the falling edge of SSI_RXCLK if the data is clocking out at the falling edge
of SSI_RXCLK.
Figure 30-14 and Figure 30-15 on page 30-37 show the main SSI configurations. These pins support all
transmit and receive functions with continuous or gated clocks as shown. Note that gated clock
implementations do not require the use of the frame sync pins (SSI_TXFS and SSI_RXFS). In this case,
these pins also can be used as GPIO pins.
MC9328MX1
SSI_TXDAT
SSI_RXDAT
SSI_TXCLK
SSI_TXFS
SSI_RXCLK
SSI_RXFS
SSI TX/RX Internal Continuous Clock
(RXDIR=1, TXDIR=1, RFDIR=1, TFDIR=1, SYN=0)
MC9328MX1
SSI_TXDAT
SSI_RXDAT
SSI_TXCLK
SSI_TXFS
SSI_RXCLK
SSI_RXFS
SSI TX/RX External Continuous Clock
(RXDIR=0, TXDIR=0, RFDIR=0, TFDIR=0, SYN=0)
Figure 30-14. Asynchronous (SYN = 0) SSI Configurations—Continuous Clock
30-36
MC9328MX1
SSI RX Internal Continuous Clock, SSI TX External
Continuous Clock
(RXDIR=1, TXDIR=0, RFDIR=1, TFDIR=0, SYN=0)
MC9328MX1
SSI TX Internal Continuous Clock, SSI RX External
Continuous Clock
(RXDIR=0, TXDIR=1, RFDIR=0, TFDIR=1, SYN=0)
MC9328MX1 Reference Manual
SSI_TXDAT
SSI_RXDAT
SSI_TXCLK
SSI_TXFS
SSI_RXCLK
SSI_RXFS
SSI_TXDAT
SSI_RXDAT
SSI_TXCLK
SSI_TXFS
SSI_RXCLK
SSI_RXFS
MOTOROLA