Data Access To 32-Bit Peripherals; Table 7-15 Core And 16-Bit Peripheral Register Content (Big Endian) - Motorola DragonBall MC9328MX1 Reference Manual

Table 7-14. Core and 16-Bit Peripheral Register Content (Little Endian) (Continued)
Table 7-15. Core and 16-Bit Peripheral Register Content (Big Endian)

7.3.3 Data Access to 32-Bit Peripherals

The followings codes are executed with the ARM core set to big and little endian modes.
LDR
LDR
LDR
STRB
STRB
STRH
STR
LDRB
LDRB
LDRH
LDR
The Table 7-16 and Table 7-17 on page 7-20 illustrate the difference in the 32-bit peripheral register
content.
MOTOROLA
Address Peripheral Registers
Address
r3
r4
r5
r6
Address Peripheral Registers
0
2
4
6
Address
r3
r4
r5
r6
r0, =0x11223344
r1, =0x55667788
r2, =32BIT_PERIPHERAL_ADDRESS
r0, [r2, #0x0]
r1, [r2, #0x1]
r0, [r2, #0x2]
r1, [r2, #0x4]
r3, [r2, #0x0]
r4, [r2, #0x1]
r5, [r2, #0x2]
r6, [r2, #0x4]
AHB to IP Bus Interface (AIPI)
Core Registers
00 00 00 44
00 00 00 88
00 00 33 44
55 66 77 88
44 88 –
33 44 –
55 66 –
77 88 –
Core Registers
00 00 00 44
00 00 00 88
00 00 33 44
55 66 77 88
Programming Example
7-19