Table 30-16 Ssi Bit And Frame Clock As A Function Of Psr And Pm In Normal Mode; Table 30-17 Ssi Sys, Bit And Frame Clock In Master Mode - Motorola DragonBall MC9328MX1 Reference Manual

Table 30-16 shows various combinations of the PSR and PM fields that achieve different bit clock
frequencies.
Table 30-16. SSI Bit and Frame Clock as a Function of PSR and PM in Normal Mode
System PLL output System Clock
in the clock
Controller Module
(MHz)
96
96
96
96
96
96
96
96
96
96
Table 30-17 shows the effect of changing the clock controller divider value to generate SYS_CLK and bit
clock frequencies close to the ideal. In these examples, master mode was selected by setting the I
Select (I2S_MODE1 and I2S_MODE0) bits in the SCSR to 01, or individually programming the SSI into
network, synchronous, and transmit internal modes.
Table 30-17. SSI Sys, Bit and Frame Clock in Master Mode
Ideal Ideal
Sampling Bit Clock
Rate Frequency
(kHz) (kHz)
8.0 256.0
11.025 352.8
16.00 512.0
22.05 705.6
32.00 1024.0
44.10 1411.0
48.00 1536.0
MOTOROLA
PerCLK3
(MHz)
Divider
Input to
PCLKDIV3
the SSI
(7 Bit)
Module
15 6.4
10 9.6
20 4.8
5 19.2
5 19.2
2 48.0
1 96.0
1 96.0
1 96.0
1 96.0
CRM Clock
Ideal Controller
SYS_CLK Divider
Frequency Value
(MHz) (with 96
MHz input)
2.048 47
2.822 32
4.096 23
5.644 17
8.192 12
11.289 9
12.288 8
Synchronous Serial Interface (SSI)
Actual Bit_Clk
Frequency
PSR
PM [7:0]
(0 or 1)
SSI_TXCLK,
SSI_RXCLK
1 24(0x18)
1 24(0x18)
0 74(0x4A)
0 74(0x4A)
0 37(0x25)
0 46(0x2E)
0 46(0x2E)
0 23(0x0F)
0 11(0x0B)
0 5(0x05)
Actual
SYS_CLK
PerCLK3
Frequency
(MHz)
(MHz)
SSI_RXCLK
2.043 2.043
3.000 3.000
4.173 4.173
5.647 5.647
8.000 8.000
10.677 10.677
12.000 12.000
Programming Model
Ideal Bit_Clk
(kHz) Frequency
(kHz)
8.0 8.0
12.0 12.0
16.0 16.0
64.0 64.0
126.3 128.0
255.3 256.0
510.6 512.0
1000.0 1024
2000.0 2048
4000.0 4096
2
S Mode
Actual Actual
Bit Clock Sampling
Frequency Rate
(kHz) (kHz)
SSI_TXCLK SSI_TXFS
255.32 7.98
375.00 11.72
510.64 15.96
705.88 22.06
1000.0 31.25
1334.63 41.71
1500.00 48.88
30-29