Table 20-5 Mmc/Sd Clock Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Table 20-5. MMC/SD Clock Control Register Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–6
ENDIAN ENDIAN FIFO Mode Selection—Setting this bit selects
Bit 5 the Endian mode of the FIFO.
Reserved Reserved—This bit is reserved and should read 0.
Bit 4
MMCSD_RESET MMCSD Reset—Resets the MMC/SD module.
Bit 3
MMCSD_ENABLE MMC/SD Enable—Enables/Disables the MMC/SD
Bit 2 module. When the module is disabled, the clock source
and all internal operations are halted.
START_CLK Start Clock—Starts the MMC/SD module clock. The
Bit 1 MMCSD_ENABLE bit must be set for START_CLK to
have any meaning. When START_CLK is changed while
the MMC/SD module is in a transmission period, the
status of the operation determines when the clock is
started. Otherwise, the clock begins immediately. Setting
a value of
Note: A transmission period is defined as the time from
a card data-access-related command is submitted to the
end of the data access operation.
STOP_CLK Stop Clock—Stops the MMC/SD clock. The
Bit 0 MMCSD_ENABLE bit must be set for STOP_CLK to have
any meaning. When STOP_CLK is changed while the
MMC/SD module is in a transmission period, the status of
the operation determines when the clock is stopped.
Otherwise, the clock halts immediately. Setting a value of
11
Note: A transmission period is defined as the time from
a card data-access-related command is submitted to the
end of the data access operation.
MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD)
Description
on Bits 1:0 is prohibited.
11
on Bits 1:0 is prohibited.
Programming Model
Settings
0 = Little endian
1 = Big endian
0 = No effect
1 = Reset the MMC/SD module
0 = Disable MMC/SD module
1 = Enable MMC/SD module
0 = MMC/SD clock inactive
1 = MMC/SD clock active
0 = MMC/SD clock active
1 = MMC/SD clock stopped
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