Motorola DragonBall MC9328MX1 Reference Manual page 519

block_read(rca, nob, addr_h, addr_l, buswidth)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
while(!Ready for data in card status is true)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
}
write_reg(NOB, <nob>);
send_cmd_wait_resp(SET_BLOCKLEN, 0x00, 0x0200, 0x01, 0x40);
if(buswidth==4-bit mode)
{
send_cmd_wait_resp(APP_CMD, rca, 0x0, 0x01, 0x40);
send_cmd_wait_resp(SET_BUS_WIDTH, 0x00, 0x02, 0x01, 0x40);
}
// Configure the DMA for FIFO read operation (BUFFER_ACCESS, SDRAM_ADDR, nob);
// Set DMA source address = BUFFER_ACCESS
// Set DMA target address = SDRAM_ADDR
// Set DMA total byte transfer = nob
// Set DMA burst depth = 8 if 1-bit mode, = 32 if 4-bit mode
if(nob==1)
send_cmd_wait_resp(READ_SINGLE_BLOCK, addr_h, addr_l, 0x09, 0x40);
else
send_cmd_wait_resp(READ_MULTIPLE_BLOCK, addr_h, addr_l, 0x09, 0x40);
if(buswidth==4-bit mode)
{
for(i=0;i<(nob*8);i++)
{
while(!FIFO full in STATUS);// polling instead of irq or dma req
for(j=0;j<32;j++)
{
SDRAM_ADDR[i*32+j] = BUFFER_ACCESS;
}
send_cmd_wait_resp(IO_RW_DIRECT, arg_h, arg_l, 0x5, 0x40);
}
}
else// 1-bit mode
{
for(i=0;i<(nob*32);i++)
{
while(!FIFO full in STATUS);// polling instead of irq or dma req
for(j=0;j<8;j++)
{
SDRAM_ADDR[i*8+j] = BUFFER_ACCESS;
}
send_cmd_wait_resp(IO_RW_DIRECT, arg_h, arg_l, 0x5, 0x40);
}
}
while(!Data Transfer Done in STATUS true);
while(!card bus is stop);
if(nob > 1)
{
send_cmd_wait_resp(STOP_TRANS, 0x00, 0x00, 0x41, 0x40);
}
}
MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD)
Code Example 20-10. Block_Read with Polling
Functional Example for the MMC/SD Module
20-41