Interrupt Instructions - Motorola HC12 Refrence Manual

5.21 Interrupt Instructions

Interrupt instructions handle transfer of control to a routine that performs a critical task.
Software interrupts are a type of exception.
covers interrupt exception processing in detail.
The SWI instruction initiates synchronous exception processing. First, the return PC
value is stacked. After CPU context is stacked, execution continues at the address
pointed to by the SWI vector.
Execution of the SWI instruction causes an interrupt without an interrupt service re-
quest. SWI is not inhibited by global mask bits I and X in the CCR, and execution of
SWI sets the I mask bit. Once an SWI interrupt begins, maskable interrupts are inhib-
ited until the I bit in the CCR is cleared. This typically occurs when an RTI instruction
at the end of the SWI service routine restores context.
The CPU12 uses the software interrupt for unimplemented opcode trapping. There are
opcodes in all 256 positions in the page 1 opcode map, but only 54 of the 256 positions
on page 2 of the opcode map are used. If the CPU attempts to execute one of the un-
implemented opcodes on page 2, an opcode trap interrupt occurs. Traps are essen-
tially interrupts that share the $FFF8:$FFF9 interrupt vector.
The RTI instruction is used to terminate all exception handlers, including interrupt ser-
vice routines. RTI first restores the CCR, B:A, X, Y, and the return address from the
stack. If no other interrupt is pending, normal execution resumes with the instruction
following the last instruction that executed prior to interrupt.
Table 5-22 is a summary of interrupt instructions.
Mnemonic
RTI
SWI
TRAP
MOTOROLA
5-18
Table 5-22 Interrupt Instructions
Function
Return from Interrupt
Software Interrupt
Software Interrupt
INSTRUCTION SET OVERVIEW
SECTION 7 EXCEPTION PROCESSING
Operation
) ⇒ CCR; (SP) + $0001 ⇒ SP
(M
(SP)
) ⇒ B : A; (SP) + $0002 ⇒ SP
(M : M
(SP) (SP+1)
) ⇒ X
(M : M : X
(SP) (SP+1) H
) ⇒ PC
(M : M : PC
(SP) (SP+1) H
) ⇒ Y
(M : M : Y
(SP) (SP+1) H
⇒
: RTN
SP – 2 SP; RTN
H
⇒
: Y
SP – 2 SP; Y
H
⇒
: X
SP – 2 SP; X
H
⇒
SP; B : A
SP – 2
⇒
SP – 1 SP; CCR
⇒
: RTN
SP – 2 SP; RTN
H
⇒
: Y
SP – 2 SP; Y
H
⇒
: X
SP – 2 SP; X
H
⇒
SP; B : A
SP – 2
⇒
SP – 1 SP; CCR
; (SP) + $0004 ⇒ SP
L
; (SP) + $0002 ⇒ SP
L
; (SP) + $0004 ⇒ SP
L
⇒
: M
M
L (SP) (SP+1)
⇒
: M
M
L (SP) (SP+1)
⇒
: M
M
L (SP) (SP+1)
⇒
: M
M
(SP) (SP+1)
⇒
M
(SP)
⇒
: M
M
L (SP) (SP+1)
⇒
: M
M
L (SP) (SP+1)
⇒
: M
M
L (SP) (SP+1)
⇒
: M
M
(SP) (SP+1)
⇒
M
(SP)
CPU12
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