Motorola DragonBall MC9328MX1 Reference Manual page 245

Table 13-2. DMA Module Register Memory Map (Continued)
DMA Request Time-Out Status Register
DMA Transfer Error Status Register
DMA Buffer Overflow Status Register
DMA Burst Time-Out Control Register
Channel 0 Source Address Register
Channel 0 Destination Address Register
Channel 0 Request Source Select Register
Channel 0 Request Time-Out Register
Channel 0 Bus Utilization Control Register
Channel 1 Source Address Register
Channel 1 Destination Address Register
Channel 1 Request Source Select Register
Channel 1 Request Time-Out Register
Channel 1 Bus Utilization Control Register
Channel 2 Source Address Register
Channel 2 Destination Address Register
Channel 2 Request Source Select Register
Channel 2 Request Time-Out Register
Channel 2 Bus Utilization Control Register
MOTOROLA
Description
2D Memory Registers
W-Size Register A
X-Size Register A
Y-Size Register A
W-Size Register B
X-Size Register B
Y-Size Register B
Channel Registers
Channel 0 Count Register
Channel 0 Control Register
Channel 0 Burst Length Register
Channel 1 Count Register
Channel 1 Control Register
Channel 1 Burst Length Register
Channel 2 Count Register
Channel 2 Control Register
Channel 2 Burst Length Register
DMA Controller
Programming Model
Name Address
DRTOSR 0x00209010
DSESR 0x00209014
DBOSR 0x00209018
DBTOCR 0x0020901C
WSRA 0x00209040
XSRA 0x00209044
YSRA 0x00209048
WSRB 0x0020904C
XSRB 0x00209050
YSRB 0x00209054
SAR0 0x00209080
DAR0 0x00209084
CNTR0 0x00209088
CCR0 0x0020908C
RSSR0 0x00209090
BLR0 0x00209094
RTOR0 0x00209098
BUCR0 0x00209098
SAR1 0x002090C0
DAR1 0x002090C4
CNTR1 0x002090C8
CCR1 0x002090CC
RSSR1 0x002090D0
BLR1 0x002090D4
RTOR1 0x002090D8
BUCR1 0x002090D8
SAR2 0x00209100
DAR2 0x00209104
CNTR2 0x00209108
CCR2 0x0020910C
RSSR2 0x00209110
BLR2 0x00209114
RTOR2 0x00209118
BUCR2 0x00209118
13-5