Table 13-18 Dma_Eobo_Cnt And Dma_Eobi_Cnt Settings - Motorola DragonBall MC9328MX1 Reference Manual

DMA Controller
Table 13-17. Channel Control Registers Description (Continued)
Name
FRC Force a DMA Cycle—Forces a DMA cycle to occur. FRC
Bit 1 always reads 0.
CEN DMA Channel Enable—Enables/Disables the DMA channel.
Bit 0
Note:
1. Program all of the channel settings before enabling the
channel.
2. To restart a channel, clear CEN, and then set CEN to
When the source mode is set to end-of-burst enable FIFO, the burst length is determined by the input
signals DMA_EOBI and DMA_EOBI_CNT, and the DMA burst (from peripheral to memory) can be
terminated only by disabling the channel (clearing the corresponding CEN bit in channel control register).
The count register (CNTR0-CNTR10) becomes read-only and indicates the number of bytes being
transferred. This setting is typically used when the channel is configured to transfer data from an endpoint
FIFO of a USB device to an endpoint data packet buffer in system memory.
When the destination mode is set to end-of-burst enable FIFO, the channel operates the same as in normal
FIFO mode, the only difference is that at the end of each burst, the DMA controller generates a
DMA_EOBO and DMA_EOBO_CNT signal to the peripheral. This setting is typically used when the I/O
channel is configured to transfer data from an endpoint data packet buffer in system memory to an
endpoint FIFO of a USB device.
Table 13-18. DMA_EOBO_CNT and DMA_EOBI_CNT Settings
13-24
Description
DMA_EOBI_CNT [1:0] or
DMA_EOBO_CNT [1:0]
00
01
10
11
MC9328MX1 Reference Manual
0 = No effect
1 = Force DMA cycle
0 = Disables the DMA channel
1 = Enables the DMA channel
1.
Number of Bytes Per Transfer
4
1
2
3
Settings
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