Table 18-7 Spi 1 Interrupt Control/Status Register And Spi 2 Interrupt Control/Status Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Integrated portable system processor
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Serial Peripheral Interface Modules (SPI 1 and SPI 2)
18.3.4 Interrupt Control/Status Registers
The SPI interrupt control status registers allow the user to enable various interrupt signals and monitor the
status of those interrupts.
INTREG1
INTREG2
BIT
31
30
29
TYPE
r
r
r
0
0
0
RESET
BIT
15
14
13
BOEN ROEN RFEN RHEN RREN TFEN THEN TEEN
TYPE
rw
rw
rw
0
0
0
RESET
Table 18-7. SPI 1 Interrupt Control/Status Register and
Name
Reserved
Reserved—These bits are reserved and should read 0.
Bits 31–16
BOEN
Bit Count Overflow Interrupt Enable—Enables/Disables the
Bit 15
Bit Count Overflow Interrupt.
ROEN
RXFIFO Overflow Interrupt Enable—Enables/Disables the
BIT 14
RXFIFO Overflow Interrupt.
RFEN
RXFIFO Full Interrupt Enable—Enables/Disables the
Bit 13
RXFIFO Full Interrupt.
RHEN
RXFIFO Half Interrupt Enable—Enables/Disables the
Bit 12
RXFIFO Half-Full Interrupt.
RREN
RXFIFO Data Ready Interrupt Enable—Enables/Disables
Bit 11
the RXFIFO Data Ready Interrupt.
TFEN
TXFIFO Full Interrupt Enable—Enables/Disables the
Bit 10
TXFIFO Full Interrupt.
THEN
TXFIFO Half Interrupt Enable—Enables/Disables the
Bit 9
TXFIFO Half-Empty Interrupt.
TEEN
TXFIFO Empty Interrupt Enable—Enables/Disables the
Bit 8
TXFIFO Empty Interrupt.
18-10
SPI 1 Interrupt Control/Status Register
SPI 2 Interrupt Control/Status Register
28
27
26
25
r
r
r
r
0
0
0
0
12
11
10
9
rw
rw
rw
rw
0
0
0
0
SPI 2 Interrupt Control/Status Register Description
Description
MC9328MX1 Reference Manual
24
23
22
21
r
r
r
r
0
0
0
0
0x0000
8
7
6
5
BO
RO
RF
rw
rw
rw
rw
0
0
0
0
0x0000
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
Addr
0x0021300C
0x0021900C
20
19
18
17
r
r
r
r
0
0
0
0
4
3
2
1
RH
RR
TF
TH
rw
rw
rw
rw
0
0
0
0
Settings
MOTOROLA
16
r
0
0
TE
rw
0

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