Figure 24-7 Off-Page Single Read Timing Diagram (32-Bit Memory); Figure 24-8 On-Page Single Read Timing Diagram (32-Bit Memory) - Motorola DragonBall MC9328MX1 Reference Manual

SDRAM Memory Controller
must make sure to program the SDRAM memory's mode control register for single burst writes for proper
operation. The SDRAM controller does, however, have the capability to issue "single-clock-cycle" writes.
This is different than the traditional burst writes, where the WRITE command and column address are
presented on the bus during the first write data, and the SDRAM memory internally increments its address.
In the case of the MC9328MX1, each data to be written to the SDRAM is accompanied with both the
WRITE command and the associated column address that is being written to. This still achieves the same
bandwidth that the burst write would. However, to take advantage of this feature, the data cache of the
ARM920T core must be enabled and the MMU set up with a page table such that the desired region of the
SDRAM memory map is cacheable. Also, the SDRAM controller does not issue a burst terminate
command after the end of a series of burst write, it simply discontinues the WRITE command.
SDCLK
ADDR
RAS,
CAS,
SDWE
CSDx
DATA
Figure 24-7. Off-Page Single Read Timing Diagram (32-Bit Memory)
SDCLK
ADDR
RAS,
CAS,
SDWE
CSDx
DATA
Figure 24-8. On-Page Single Read Timing Diagram (32-Bit Memory)
24-20
ROW COL
A A
t Minimum
RCD
ACT READ
COLUMN COLUMN
A A
CAS Latency
READ TBST
MC9328MX1 Reference Manual
COL
A
t
CL
TBST NOP NOP
DATA
A
NOP NOP
DATA
A
COL
B
NOP READ
COLUMN
B
NOP READ
MOTOROLA