Motorola DragonBall MC9328MX1 Reference Manual page 226

External Interface Module (EIM)
Table 11-7. EIM Configuration Register Description (Continued)
Name
BCM Burst Clock Mode—Selects the burst clock
Bit 2 mode of operation.
BCM is cleared by a hardware reset.
Reserved Reserved—These bits are reserved and should read 0.
Bits 1–0
11-22
Description
MC9328MX1 Reference Manual
Settings
0 = The burst clock runs only when accessing a
chip select range with the SYNC bit set.
When the burst clock is not running, it
remains in a logic 0 state; when the burst
clock is running, it is configured by the BCD
and BCS bits in the chip select control
register.
1 = The burst clock runs all the time (independent
of chip select accesses).
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