Motorola DragonBall MC9328MX1 Reference Manual page 33

Figure 25-8 Start Bit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11
Figure 25-9 Parity Bit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12
Figure 25-10 Framing Error Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12
Figure 25-11 Valid Initial Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
Figure 25-12 Inverse Convention vs. Direct Convention. . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
Figure 25-13 Two Methods of SmartCard Hookup to MC9328MX1 SIM Port . . . . . . . . . 25-15
Figure 25-14 Automatic Powerdown Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16
Figure 25-15 Cyclic Redundancy Check Circuit Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 25-17
Figure 25-16 Suggested T = 1, EMV, and Geldkate Compliant SIM Initialization. . . . . . . 25-53
Figure 26-1 General-Purpose Timers Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1
Figure 27-1 General Connections for a UART with a Modem . . . . . . . . . . . . . . . . . . . . . . 27-6
Figure 27-2 UART Block Diagram and Clock Generation Diagram . . . . . . . . . . . . . . . . . . 27-9
Figure 27-3 Transmitter FIFO Empty Interrupt Suppression Flow Chart . . . . . . . . . . . . . 27-11
Figure 27-4 Baud Rate Detection Protocol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-16
Figure 27-5 Majority Vote Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-52
Figure 27-6 Baud Rate Detection of Divisor = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-52
Figure 28-1 USB Device Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3
Figure 28-2 USB Module Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5
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Figure 29-1 I C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
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Figure 29-2 I C Standard Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
Figure 29-3 Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4
Figure 29-4 Synchronized Clock SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4
Figure 29-5 Flow Chart of Typical I
Figure 30-1 MC9328MX1 Input/Output Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2
Figure 30-2 SSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3
Figure 30-3 SSI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4
Figure 30-4 SSI Transmit Clock Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 30-5
Figure 30-5 SSI Transmit Frame Sync Generator Block Diagram . . . . . . . . . . . . . . . . . . . 30-5
Figure 30-6 Transmit Data Path (TXBIT0 = 0, TSHFD = 0). . . . . . . . . . . . . . . . . . . . . . . 30-10
Figure 30-7 Transmit Data Path (TXBIT0 = 0, TSHFD = 1). . . . . . . . . . . . . . . . . . . . . . . 30-11
Figure 30-8 Transmit Data Path (TXBIT0 = 1, TSHFD = 0). . . . . . . . . . . . . . . . . . . . . . . 30-11
Figure 30-9 Transmit Data Path (TXBIT0 = 1, TSHFD = 1). . . . . . . . . . . . . . . . . . . . . . . 30-11
Figure 30-10 Receive Data Path (RXBIT0 = 0, RSHFD = 0) . . . . . . . . . . . . . . . . . . . . . . . 30-14
Figure 30-11 Receive Data Path (RXBIT0 = 0, RSHFD = 1) . . . . . . . . . . . . . . . . . . . . . . . 30-14
Figure 30-12 Receive Data Path (RXBIT0 = 1, RSHFD = 0) . . . . . . . . . . . . . . . . . . . . . . . 30-14
Figure 30-13 Receive Data Path (RXBIT0 = 1, RSHFD = 1) . . . . . . . . . . . . . . . . . . . . . . . 30-15
Figure 30-14 Asynchronous (SYN = 0) SSI Configurations-Continuous Clock. . . . . . . . 30-36
Figure 30-15 Synchronous SSI Configurations-Continuous and Gated Clock . . . . . . . . . 30-37
Figure 30-16 Serial Clock and Frame Sync Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-37
MOTOROLA
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C Interrupt Routine . . . . . . . . . . . . . . . . . . . . . . . . . 29-17
List of Figures xxxiii