Motorola DragonBall MC9328MX1 Reference Manual page 962

R/W bit, 16-79
SPI_READ_ADDR register, 16-78
SPI_STATUS register
DONE bit, 16-81
SPI_STATUS register, 16-81
SPI_WORD0 register
BYTE0 field, 16-74
BYTE1 field, 16-74
WORD0 field, 16-73
SPI_WORD0 register, 16-73
SPI_WORD1 register
WORD1 field, 16-74
SPI_WORD1 register, 16-74
SPI_WORD2 register
BYTE4 field, 16-76
BYTE5 field, 16-76
WORD2 field, 16-75
SPI_WORD2 register, 16-75
SPI_WORD3 register
BYTE6 field, 16-76
BYTE7 field, 16-77
WORD3 field, 16-76
SPI_WORD3 register, 16-76
SPI_WRITE_ADDR register
ADDRESS field, 16-77
R/W bit, 16-77
R/W bit, 16-78
SPI_WRITE_ADDR register, 16-77
SRCR register, 30-24
SRST bit, 25-22
SSA register
SSA field, 19-20
SSA register, 19-20
SSI
architecture, 30-1
calculating bit clock from input clock, 30-28
clock and frame sync generation, 30-4
clocking, 30-4
data and control pins
SSI_RXCLK pin, 30-35
SSI_RXDAT pin, 30-35
SSI_RXFS pin, 30-36
SSI_TXCLK pin, 30-35
SSI_TXDAT pin, 30-35
SSI_TXFS pin, 30-36
data and control pins, 30-35
data bit shifting configuration, 30-10
external frame and clock operation, 30-44
2
I S mode selection, 30-19
introduction, 30-1
operating modes
gated clock mode, 30-43
network mode, 30-41
normal mode, 30-39
Index-xx
operating modes, 30-38
pin config software example, 30-7
pin configuration, 30-5
programming model, 30-7
receive data register, 30-12
receive FIFO register, 30-12
receive shift register, 30-13
register memory map, 30-7
reset and initialization procedure, 30-44
transmit FIFO register, 30-9
transmit shift register, 30-9
SSI clocking
master / synchronous mode, 30-4
normal input mode, 30-4
SSI control/status register, see SCSR register
SSI FIFO control/status register, see SFCSR register
SSI option register, see SOR register
SSI receive configuration register, see SRCR register
SSI time slot register, see STSR register
SSI transmit configuration register, see STCR register
SSR_A register, 32-18
SSR_B register, 32-18
SSR_C register, 32-18
SSR_D register, 32-18
SSR_x register
SSR field, 32-18
Statistic data generation, 31-13
STATUS register
APPL_BUFF_FE bit, 20-17
APPL_BUFF_FF bit, 20-17
BUF_ADDR field, 16-28
CARD_BUS_CLK_RUN bit, 20-17
CARD_PRESENCE bit, 20-16
CRC_READ_ERR bit, 20-17
CRC_WRITE_ERR bit, 20-17
CRC16 bit, 16-28
DATA_TRANS_DONE bit, 20-17
END_CMD_RESP bit, 20-16
HEC8 bit, 16-28
MS bit, 16-28
MS2LSB field, 16-28
NREC bit, 16-28
REC bit, 16-28
REC1 bit, 16-28
RESP_CRC_ERR bit, 20-17
SDIO_INT_ACTIVE bit, 20-16
STATE field, 16-28
TIME_OUT_READ bit, 20-18
TIME_OUT_RESP bit, 20-18
WR_CRC_ERROR_CODE field, 20-17
WRITE_OP_DONE bit, 20-16
STATUS register, 16-27
Status register, see STATUS register
STCR register, 30-21
MC9328MX1 Reference Manual
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