Operation - Motorola DragonBall MC9328MX1 Reference Manual

Interrupt Controller (AITC)
• Detects all pending interrupts and distinguishes by priority level
• Independently enables or disables any interrupt source
• Provides a mechanism for software to schedule an interrupt
• Supports a maximum of 16 software controlled priority levels for normal interrupts and priority
masking

10.2 Operation

The interrupt controller consists of a set of control registers and associated logic to perform interrupt
masking, priority support, and hardware acceleration of normal interrupts.
The interrupt source registers (INTSRCH and INTFRCL) are a pair of 32-bit status registers with a single
interrupt source associated with each of the 64 bits. An interrupt line or set of interrupt lines is routed from
each interrupt source to the INTSRCH or INTFRCL register. This configuration allows the ARM920T
processor of the MC9328MX1 to monitor a maximum of 64 distinct interrupt sources.
Interrupt requests can be forcibly asserted through the interrupt force registers (INTFRCH and INTFRCL).
Each bit in these registers is logically ORed with the corresponding hardware request line prior to input to
the INTSRCH or INTFRCL registers.
There is a corresponding set of interrupt enable registers (INTENABLEH and INTENABLEL), each
32 bits wide, that allow individual bit masking of the INTSRCH and INTFRCL registers. There is also a
corresponding set of interrupt type registers (INTTYPEH and INTTYPEL) that selects whether an
interrupt source generates a normal or fast interrupt to the ARM920T processor.
There is a corresponding set of normal interrupt pending registers (NIPNDH and NIPNDL) that indicate
pending normal interrupt requests, and are equivalent to the logical AND of the interrupt source registers
(INTSRCH and INTSRCL), the interrupt enable registers (INTENABLEH and INTENABLEL), and the
NOT of the interrupt type registers (INTTYPEH and INTTYPEL). The NIPNDH and NIPNDL register
bits are bit-wise NORed together to generate the nIRQ signal that is routed to the ARM920T processor.
This ARM920T processor input signal is maskable by the normal interrupt disable bit (I bit) in the program
status register (CPSR). The normal interrupt vector register (NIVECSR) indicates the vector index of
highest priority pending normal interrupt.
There is a corresponding set of fast interrupt pending registers (FIPNDH and FIPNDL) that indicate
pending fast interrupt requests, and are equivalent to the logical AND of the interrupt source registers
(INTSRCH and INTSRCL), the interrupt enable registers (INTENABLEH and INTENABLEL), and the
interrupt type registers (INTTYPEH and INTTYPEL). The FIPNDH and FIPNDL register bits are bit-wise
NORed together to generate the nFIQ signal that is routed to the ARM920T processor. This ARM920T
processor input signal is maskable by the fast interrupt disable bit (F bit) in the CPSR. The fast interrupt
vector register (FIVECSR) indicates the vector index of highest priority pending fast interrupt.
All interrupt controller registers are readable and writable in supervisor mode only. Writes attempted to
read-only registers are ignored. These registers must be written with 32-bit stores only.
The INTFRCH and INTFRCL registers are provided for software generation of interrupts. By enabling
interrupts for these bit positions, software can force an interrupt request. This register also provides an
alternate method of interrupt assertion for debugging hardware interrupt service routines.
The interrupt requests are prioritized in the following order:
1. Fast interrupt requests, in order of highest number
2. Normal interrupt requests, in order of highest priority level, then highest source number
with the same priority
10-2 MC9328MX1 Reference Manual MOTOROLA