Ssi Receive Shift Register; Table 30-6 Data Bit Shifting Configuration - Motorola DragonBall MC9328MX1 Reference Manual

30.3.6 SSI Receive Shift Register

The SSI Receive Shift Register (RXSR) is a 16-bit shift register that contains the data being received from
the SSI_RXDAT pin. When the register is full, received data fills the receive FIFO.
When a continuous clock is used, data is shifted in by the selected (internal/external) bit clock when the
associated (internal/external) frame sync is asserted. When a gated clock is used, data is shifted in from the
SSI_TXDAT pin by the selected (internal/external) gated clock.
The Receive shift direction (RSHFD) bit and Receive bit position(RXBIT0) in the SRCR determines how
the data is stored. Table 30-6 contains all of the information about data bit shifting configurations and
Figure 30-10 through Figure 30-13 visually the data path for each configuration.
The WL bits in the SSI Receive Clock Control Register (SRCCR) determine the number of bits to be
shifted in from the SSI_RXDAT pin. This word length can be 8, 10, 12, or 16 bits. When receiving 8, 10,
or 12 bits of data, 0s are appended to the end of the data string to fill the 16-bit register.
RXBIT0
0
0
1
1
MOTOROLA
Table 30-6. Data Bit Shifting Configuration
RSHFD WL[1:0]
0 00 Bit 15 (MSB) first, bit 8 (LSB) last
01 Bit 15 (MSB) first, bit 6 (LSB) last
10 Bit 15 (MSB) first, bit 4 (LSB) last
11 Bit 15 (MSB) first, bit 0 (LSB) last
1 00 Bit 8 (MSB) first, bit 15 (LSB) last
01 Bit 6 (MSB) first, bit 15 (LSB) last
10 Bit 4 (MSB) first, bit 15 (LSB) last
11 Bit 0 (MSB) first, bit 15 (LSB) last
0 00 Bit 0 (MSB) first, bit 7 (LSB) last
01 Bit 0 (MSB) first, bit 9 (LSB) last
10 Bit 0 (MSB) first, bit 11 (LSB) last
11 Bit 0 (MSB) first, bit 15 (LSB) last
1 00 Bit 7 (MSB) first, bit 0 (LSB) last
01 Bit 9 (MSB) first, bit 0 (LSB) last
10 Bit 11 (MSB) first, bit 0 (LSB) last
11 Bit 15 (MSB) first, bit 0 (LSB) last
Synchronous Serial Interface (SSI)
Programming Model
Shifting to bit
30-13