Table 29-8 I2Dr Register Description - Motorola DragonBall MC9328MX1 Reference Manual

2
I C Module
2
29.6.5 I C Data I/O Register
2
The I C Data I/O Register (I2DR) contains the data received or the data to be transmitted during I/O
operations. In transmission mode, this value is sent out after the receiving device sends an acknowledge
signal. In master-receive mode, the last byte received is held in this register. Reading this register initiates
the transfer of the next byte of receive data. In slave mode, the same function is available after the device is
addressed.
I2DR
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–8
2
D I C Data—Holds last data byte received or next data byte to be transferred.
Bits 7–0
2
29.7 I C Programming Examples
This section describes programming sequences for I
post-transfer software response, STOP signalling, and repeated START generation. The flowchart in
Figure 29-5 on page 29-17 illustrates an interrupt routine.
29-14
2
I C Data I/O Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
r r r r
0 0 0 0
Table 29-8. I2DR Register Description
2
C, including initialization, START signalling,
MC9328MX1 Reference Manual
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
r rw rw rw rw
0 0 0 0 0
0x0000
Description
Addr
0x00217010
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
D
rw rw rw rw
0 0 0 0
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