Peripheral Access Registers; Table 7-9 Psr Data Bus Size Encoding - Motorola DragonBall MC9328MX1 Reference Manual

AHB to IP Bus Interface (AIPI)

7.2.2 Peripheral Access Registers

These registers are used to tell the AIPI whether or not the IP bus peripheral corresponding to the bit
location in the register may be accessed in user mode. If the peripheral may be accessed in supervisor
mode only and a user mode access is attempted an abort will be generated and no IP bus activity occurs. If
the peripheral can be accessed in user mode, then the IPS_SUPERVISOR_ACCESS bit reflects whether
the attempted access is in supervisor or user mode and the peripheral itself can decide whether to accept a
user access (if one is attempted) or issue an error response.
The least significant bit in the PAR is a read only bit as it governs the AIPI registers themselves. It is set to
indicate supervisor access only. Bits 31 through 16 in both registers are preset to 1 and the fields are
reserved and can only be read.
PAR_1
PAR_2
BIT 31 30 29
TYPE
1 1 1
PAR_1
RESET
1 1 1
PAR_2
RESET
BIT 15 14 13
TYPE rw rw rw
1 1 1
PAR_1
RESET
1 1 1
PAR_2
RESET
7-14
Table 7-9. PSR Data Bus Size Encoding
PSR[1:0] Bits
PSR1[x] PSR0[x]
0 0
0 1
1 0
1 1
AIPI1 Peripheral Access Register
AIPI2 Peripheral Access Register
28 27 26 25
1 1 1 1
1 1 1 1
12 11 10 9
ACCESS
rw rw rw rw
1 1 1 1
1 1 1 1
MC9328MX1 Reference Manual
IP Bus Peripheral Size [x]
(module_en [x])
8-bit
16-bit
32-bit
Unoccupied
24 23 22 21
1 1 1 1
0xFFFF
1 1 1 1
0xFFFF
8 7 6 5
rw rw rw rw
1 1 1 1
0xFFFF
1 1 1 1
0xFFFF
Addr
0x00200008
0x00210008
20 19 18 17
1 1 1 1
1 1 1 1
4 3 2 1
rw rw rw rw
1 1 1 1
1 1 1 1
MOTOROLA
16
1
1
0
r
1
1