Usb Control Register; Table 28-7 Usb Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Integrated portable system processor
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28.3.4 USB Control Register

The USB Control Register configures numerous features of the USB module.
USB_CTRL
BIT
31
30
29
TYPE
r
r
0
0
0
RESET
BIT
15
14
13
TYPE
r
r
0
0
0
RESET
Name
Reserved
Reserved—These bits are reserved and should read 0.
Bits 31–7
CMD_OVER
Command Over—Indicates status of command
Bit 6
processing. See Table 28-8 for more information.
CMD_OVER clears automatically after the UDC core has
completed the status phase of a control transfer.
CMD_ERROR
Command Error—Indicates if an error was encountered
Bit 5
during processing of a device request. See Table 28-8 for
more information. CMD_OVER and CMD_ERROR
combine to create the handshaking code for the status
phase of a device request transaction.
USB_SPD
USB Speed—Sets the operating speed for the USB
Bit 4
module.
Note: The USB module supports only full speed
operation of the device. Attempts to set to slow speed
results in unpredictable operation.
USB_ENA
USB Enable—Determines whether the USB module
Bit 3
responds to requests from the USB host. The USB module
comes out of reset in the disabled state. The user must
ensure that the USB endpoint configuration and USB
registers are programmed appropriately before enabling
communications. USB_ENA does not affect the underlying
UDC core, only the front-end logic's ability to communicate
with the core.
MOTOROLA
USB Control Register
28
27
26
25
24
r
r
r
r
r
r
0
0
0
0
0
12
11
10
9
8
r
r
r
r
r
r
0
0
0
0
0
Table 28-7. USB Control Register Description
Description
USB Device Port
23
22
21
20
r
r
r
r
0
0
0
0
0x0000
7
6
5
4
CMD_
CMD_
USB_
OVER
ERROR
SPD
r
rw
rw
rw
0
0
0
1
0x0010
0 = Command complete
1 = Command in process
0 = If the command was processed,
there was no error
1 = If the command was processed,
an error occurred
0 = Low speed
1 = Full speed
0 = USB module front-end logic is
disabled. All transactions to or
from the UDC are ignored.
1 = USB module front-end logic is
enabled and ready to
communicate with the host.
Programming Model
Addr
0x0021200C
19
18
17
16
r
r
r
r
0
0
0
0
3
2
1
0
USB_
UDC_
AFE_
RESUME
ENA
RST
ENA
rw
w
rw
w
0
0
0
0
Settings
28-11

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