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ARM920T Processor
4.4.2 Load and Store Instructions
The second class of instruction is load and store instructions. These instructions come in two main types:
•
Load or store the value of a single register
•
Load and store multiple register values.
Load and store single register instructions can transfer a 32-bit word, a 16-bit halfword and an 8-bit byte
between memory and a register. Byte and halfword loads might be automatically zero extended or sign
extended as they are loaded. Swap instructions perform an atomic load and store as a synchronization
primitive.
4.4.2.1 Addressing Modes
Load and store instructions have three primary addressing modes:
•
Offset
•
Pre-indexed
•
Post-indexed.
They are formed by adding or subtracting an immediate or register based offset to or from a base register.
Register-based offsets can also be scaled with shift operations. Pre-indexed and post-indexed addressing
modes update the base register with the base plus offset calculation. As the PC is a general purpose
register, a 32-bit value can be loaded directly into the PC to perform a jump to any address in the 4 Gbyte
memory space.
4.4.2.2 Block Transfers
Load and store multiple instructions perform a block transfer of any number of the general purpose
registers to or from memory. Four addressing modes are provided:
•
Pre-increment addressing
•
Post-increment addressing
•
Pre-decrement addressing
•
Post-decrement addressing.
The base address is specified by a register value (that can be optionally updated after the transfer). As the
subroutine return address and the PC values are in general-purpose registers, very efficient subroutine calls
can be constructed.
4.4.3 Branch Instructions
As well as allowing any data processing or load instruction to change control flow (by writing the PC) a
standard branch instruction is provided with 24-bit signed offset, allowing forward and backward branches
of up to 32 Mbyte.
4.4.3.1 Branch with Link
There is a Branch with Link (BL) that allows efficient subroutine calls. BL preserves the address of the
instruction after the branch in R14 (the Link Register, or LR). This allows a move instruction to put the LR
in to the PC and return to the instruction after the branch.
4-6
MC9328MX1 Reference Manual
MOTOROLA
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