Sdram Reset Initialization; Figure 24-52 Single 256 Mbit (8M X 32) Connection Diagram (Iam = 0); Table 24-32 Single 256 Mbit (8M X 32) Control Register Values (Iam = 0) - Motorola DragonBall MC9328MX1 Reference Manual

SDRAM Memory Controller
Table 24-32. Single 256 Mbit (8M x 32) Control Register Values (IAM = 0)
Figure 24-52. Single 256 Mbit (8M x 32) Connection Diagram (IAM = 0)
JEDEC has not issued a standard pinout and array configuration for the
256 Mbit density memories in a x32 package option. This connection
diagram is based on the PC100 Standard.

24.8.3 SDRAM Reset Initialization

SDRAM initialization must follow a defined sequence following the power-on condition. The steps are as
follows:
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP conditions
at the command inputs.
2. Maintain stable power, clock, and NOP conditions for a minimum of 200 µs.
3. Issue precharge commands for all banks either with precharge all or precharge individual
bank commands.
4. After all banks are in the idle state for a minimum time of t
commands.
5. Issue a mode register set command to initialize the mode register.
24-56
Control Field
Density
Page size
ROW
COL
DSIZ
IAM Non-bank–interleaved
SDCLK
SDCKE
A14
A13
A[12:11]
MA[11:10], A[10:2]
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
D[31:0]
MC9328MX1
NOTE:
MC9328MX1 Reference Manual
Value
32 Mbyte
1024 bytes
13
8
32 (D [31:0])
CLK
CKE
BA1
BA0
A[12:11]
A[10:0]
RAS
CAS
CS
WE
DQM3
DQM2
DQM1
DQM0
DQ[31:0]
8M x 32
SDRAM
, issue 8 or more auto-refresh
RP
MOTOROLA