System Pll Control Register 1; Table 12-13 System Pll Control Register 1 Description - Motorola DragonBall MC9328MX1 Reference Manual

Table 12-12. System PLL Control Register 0 Description (Continued)
Name
MFI Multiplication Factor (Integer Part)—Defines the integer part of the BRM
Bits 13–10 value for the MF. The MFI is decoded so that MFI < 5 results in MFI = 5.
The System PLL oscillates at a frequency determined by Equation 12-1.
Where PD is the division factor of the predivider, MFI is the integer part of the
total MF, MFN is the numerator of the fractional part of the MF, and MFD is the
denominator part of the MF. The MF is chosen to ensure that the resulting VCO
output frequency remains within the specified range. When a new value is
written into the MFI bits, the PLL loses its lock; after a time delay, the PLL
re-locks.
MFN Multiplication Factor (Numerator Part)—Defines the numerator part of the
Bits 9–0 BRM value for the MF. When a new value is written into the MFN bits, the PLL
loses its lock; after a time delay, the PLL re-locks.

12.5.4.2 System PLL Control Register 1

The System PLL control register 1 (SPCTL1) is a 32-bit read/write register in the MCU memory map that
directs the operation of the System PLL. The SPCTL1 control bits are described in this section.
SPCTL1
BIT 31 30 29
TYPE r r
0 0
RESET
BIT 15 14 13
LF
TYPE rw r
0 0
RESET
Table 12-13. System PLL Control Register 1 Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
LF Lock Flag—Indicates whether the System PLL is locked. When
Bit 15 set, the System PLL clock output is valid. When cleared, the
System PLL clock output remains at logic high.
Reserved Reserved—These bits are reserved and should read 0.
Bits 14–7
MOTOROLA
Description
System PLL Control Register 1
28 27 26 25 24
r r r r r r
0 0 0 0 0 0
12 11 10 9 8
r r r r r r
0 0 0 0 0 0
Description
Phase-Locked Loop and Clock Controller
23 22 21
r r r
0 0 0
0x0000
7 6 5
BRMO
r rw r
0 0 0
0x0000
Programming Model
Settings
0000–0101 = 5
0110 = 6
...
1111 = 15
0x000 = 0
0x001 = 1
...
0x3FE = 1022
0x3FF = Reserved
Addr
0x0021B010
20 19 18 17 16
r r r r
0 0 0 0
4 3 2 1
r r r r
0 0 0 0
Settings
0 = System PLL is not locked
1 = System PLL is locked
r
0
0
r
0
12-13